Commit graph

8801 commits

Author SHA1 Message Date
Dino Li
36164c29c1 espi: it8xxx2: enable configuration of Chromebook
This enables the below configuration so the AP and EC are able to
communicate over eSPI:

CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-02-21 22:01:48 -05:00
Jun Lin
756babfa75 soc: npcx: add support for npcx9m7f
Add new SoC npcx9m7f support for npcx9 series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-21 21:56:24 -05:00
Jun Lin
2296f1f884 dts: arm: npcx: refactor the RAM configuration
The last 2k bytes of the data RAM is used by the booter in some npcx EC
chips. This commit adds a bootloader_ram DT node to describe this
additional layout of the RAM. As a result, we can determine the total
RAM size by adding the size of flash0, sram0, and bootloader_ram.

Also, this commit moves 64k bytes from the code RAM (flash0) to the data
RAM (sram0) for npcx7m7fc because its internal flash is 512K bytes.
(In the Chromebook application, we need the code RAM size <= half of the
flash size.)

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-21 21:56:09 -05:00
Jun Lin
82a8329443 dts: npcx: change status of vsby-psl-in-list default disabled
The application may not always use the PSL mode. Change the status of
node vsby-psl-in-list default disabled. The application can override it
when it wants to use PSL hibernate.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-21 21:55:54 -05:00
Tom Burdick
1e9ada4eb9 dma: cavs: Add gpdma derivative of dw dma for cavs
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-02-21 20:59:08 -05:00
Katsuhiro Suzuki
feaf0070fc boards: riscv: hifive_unleashed: add GPIO support
This patch adds GPIO and 96board LS (Low Speed)iexpansion  connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2022-02-21 20:46:47 -05:00
Immo Birnbaum
43e94bb0f9 dts: arm: xilinx: zynqmp: Add UART1 to device tree
Add the DT node for the 2nd UART controller.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-02-21 20:45:44 -05:00
Jay Vasanth
f6394e0d54 Microchip: MEC172x: kscan driver
Update keyscan driver to support MEC172x device

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-02-21 20:44:17 -05:00
Jay Vasanth
4120a889a4 Microchip: MEC172x: watchdog driver
Update wdt driver to support MEC172x device

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-02-21 20:42:18 -05:00
BJ Chen
59cd9fd551 ITE: drivers/peci: Add PECI driver module of ITE IT8xxx2
Added the PECI driver tested with the samples/drivers/peci.

Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
2022-02-21 19:43:40 -05:00
Andrei-Edward Popa
681a57cd47 dts: arm: rpi_pico: added I2C support for Raspberry Pi Pico board
added I2C device tree nodes
based on I2C designware chip

Signed-off-by: Andrei-Edward Popa <andrei_edward.popa@upb.ro>
2022-02-21 19:42:07 -05:00
Andrei-Edward Popa
4ae0c84c49 dts: bindings: i2c: added pinctrl include for DW
added pinctrl include support for I2C designware chip

Signed-off-by: Andrei-Edward Popa <andrei_edward.popa@upb.ro>
2022-02-21 19:42:07 -05:00
Yuriy Vynnychek
4747f3ac3d dts: riscv: telink_b91: replace pinmux by pinctrl
Replaced pinmux by new pinctrl driver for Telink B91.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-02-21 19:41:44 -05:00
Sylvio Alves
6ba6894580 drivers: wdt: esp32: code refactor to use hal calls
Update WDT driver to use hal calls, which
brings proper unification among socs.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-02-21 19:40:17 -05:00
Henrik Brix Andersen
1563b2c990 dts: bindings: can: remove unused bus from CAN controller binding
Remove the unused bus statement from the common CAN controller devicetree
binding.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-02-21 19:39:14 -05:00
David Leach
8e3f1615af dts: rt11xx: Fix invalid SAI4 address
Register address definition for SAI4 was incorrect.

Signed-off-by: David Leach <david.leach@nxp.com>
2022-02-04 09:05:31 -06:00
Martí Bolívar
c0cc6c7ba2 dts: bindings: gpio-leds: improve description
This is the compatible which is used in the blinky sample, so
it's worth trying to add a better example for what you can do with it
in general in the main description.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-02-04 11:20:46 +01:00
Yonatan Schachter
a2aa02dbc8 drivers: gpio: Added support for raspberry pi
Added GPIO support for the RP2040 SoC. Only one
core is supported.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter
cd7bd5f450 drivers: serial: Added support for raspberry pi
Added a serial driver for the RP2040. Only polling
API is supported.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter
fd59038312 drivers: pinctrl: Added pinctrl driver for RPi Pico
Added a pinctrl driver for the Raspberry Pi Pico series

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2022-02-02 16:23:35 +01:00
Yonatan Schachter
db5b2780bf soc: Added support for Raspberry Pi's RP2040 SoC
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2022-02-02 16:23:35 +01:00
Jun Lin
83cbea11c7 dts: arm: npcx: fix the data RAM size
As npcx9m3f/npcx9m6f needn't share the upper 2KB of data RAM to Booter,
let's fix the data RAM size from 62KB to 64KB for them.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-02-01 08:17:57 -05:00
Hake Huang
53317c83fe dts: add missing dts config for pre-div for rt11xx
the pre-dic is not used in rt11xx series, but for driver compatible
with rt10xx we still need have it in dts

fixing: #42179

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-28 10:06:53 +01:00
Pete Dietl
cb793e3d33 stm32g4: adc: Add DTS for ADC345
Add DTS information for ADCs 3, 4, and 5 for stm32g4

Signed-off-by: Pete Dietl <petedietl@gmail.com>
2022-01-21 14:38:50 -05:00
Marius Scholtz
38d684f8f1 drivers: counter: sam: expose RC reg to DT
Exposes the RC register so that the initial value can be set in
the device tree. This is useful in the case where the timer
generates an event but an interrupt is not required.
e.g generate event to sample adc on RC register match.

Tested on Atmel SMART SAM E70 Xplained Ultra board

Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
2022-01-21 14:25:49 -05:00
Sylvio Alves
c409a4656f drivers: uart: esp32: use DEVICE_DT_INST_DEFINE()
Current uart driver implementation is incompleted regarding the
usage of DT_INST_FOREACH_STATUS_OKAY. If uart0 and uart2 are selected,
build breaks due to peripheral number ordering, which would be
0 and 1 in this case. This fix PR fix this by re-working the macros
and setting proper uart peripheral instances in DTSI, required for signal
routing configuration.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-21 13:16:55 -05:00
Hake Huang
6d621787e4 dts: rt11xx: add sai1-4 support
add sai1-4 support in rt11xx series

adjust the dts settings for sai on CM7 and CM4

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Immo Birnbaum
d6c9475fce dts: arm: xilinx: zynq7000: remove "cpus" node from SoC DT
Remove the "cpus" node from the SoC device tree. The Zynq-7000
comes with either 1 or 2 CPU cores. While all the different
models within this SoC family have different capabilities in
particular when it comes to the programmable logic part and
I/O pins, there is no difference between the XC7Zxxx (2 cores)
and XC7ZxxxS (1 core) models when it comes to the peripherals
integrated in the SoC. Therefore, it makes little sense to
add a zynq7000s.dtsi next to the existing zynq7000.dtsi whose
only difference is the CPU count. Instead, the "cpus" node,
containing the appropriate CPU core definitions for the SoC
the respective target is equipped with, shall be specified at
the board level instead.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2022-01-21 11:34:09 -05:00
Sylvio Alves
eec068b8a5 soc: esp32c3: fix cpu vendor name
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-20 13:33:29 -05:00
Sylvio Alves
16f9674049 soc: esp32c3: fix timer address case warning
DTSI address is case sensitive and timer address
isn't folowing that rule.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-20 13:33:29 -05:00
Jeremy Wood
c13ff7505c dts: add stm32h7 can binding and node
* Add can peripheral to stm32h7.dtsi.
* Add binding for m_can stm32h7 driver.

Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
2022-01-19 16:07:54 -05:00
Mahesh Mahadevan
a7998f4cff dts: Add support for NXP MXRT5xx
Add support for MXRT595S

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-19 13:35:09 -06:00
Mahesh Mahadevan
f4163ba596 dts: Update GPIO port numbers
Add more GPIO port numbers to the enum list

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-19 13:35:09 -06:00
Benedikt Schmidt
9108d83c6e soc: arm: stm32: add LPTIM1 to H735
Add one instance of LPTIM to H735 devicetree.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2022-01-19 14:15:29 -05:00
Antony Pavlov
c2c5727bf8 dts/bindings: Add binding for mti,cpu-intc
Add a simple binding for MIPS CPU interrupt controller.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-19 13:48:21 -05:00
Jordan Yates
ccdc009077 drivers: power_domain: gpio controlled domain
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-01-19 13:35:32 -05:00
Flavio Ceolin
ddfa048058 pm: Add power domain infra structure
Add support for power domains on Zephyr. Power domains are implemented
as simple devices so they can use the existent Zephyr API, for resume
and suspend sync and async and also reference count.

The pm subsystem will ensure that domains are resumed before and
suspended after devices using them. For device runtime power
management, every time the device is got or released the same actions
is done to the domain it belongs.

As domains are implemented as simple devices, it is totally acceptable
a domain belongs to another domain.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-01-19 13:35:32 -05:00
Daniel Leung
2deb825f80 dts: intel_cavs25: add an entry for the TLB driver
This adds an entry for the TLB memory management driver
on intel_cavs25.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00
Daniel Leung
9e688e3956 drivers: mm: add driver for Intel Audio DSP
This adds the driver for the memory mapping hardware
on Intel Audio DSP.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00
Daniel Leung
213fccbfe4 dts: add base binding for memory management drivers
This adds a simple base binding for memory management drivers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00
Daniel DeGrasse
48434ee1dd soc: mimxrt1170: Add power state defintions for RT1170
Adds power state definitions for RT1170. Min residency times are loosely
derived from transition times into similar power states in the datasheet

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Daniel DeGrasse
93c003fdc9 soc: mimxrt1160: Add power state definitions for RT1160
Adds power state definitions for RT1160. Min residency times are loosely
derived from transition times into similar power states in the datasheet

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Daniel DeGrasse
19bb8e2ec8 soc: rt11xx: Enable power management for RT11xx series SOCs
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:

- system reduces core voltage during sleep
- core clock can be gated in deep sleep

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Yasushi SHOJI
2e3aeaaac8 dts: Add Space Cubics as "sc"
Add Space Cubics, LLC as "sc".

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
2022-01-18 13:21:50 -05:00
Aymeric Aillet
37f5fe5e82 drivers: serial: RCar add pinctrl support
Get pin configuration from device tree to
set alternate pin function.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2022-01-18 13:04:53 -05:00
Daniel DeGrasse
b6b9453d83 boards: mimxrt1160_evk: Enable ENET
Enable 10/100M Ethernet for RT1160 EVK

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Daniel DeGrasse
594e11a540 drivers: eth_mcux: Enable specifying PHY addr for enet module
PHY addr is not always 0 on boards with multiple PHYs. Allow specifying
via devicetree.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Alexander Wachter
9a989be2bf dts: atmel: SAME70: Add can instances for SAME70
This commit adds can0 and can1 on the Atmel SAME70.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2022-01-18 10:39:55 -05:00
Alexander Wachter
6e5c8a339d drivers: can: Add frontend for Atmel SAM M_CAN controller
This commit adds a frontend for the generic Bosch m_can driver
for Atmel SAM series.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2022-01-18 10:39:55 -05:00
Henrik Brix Andersen
b6f6069b99 drivers: can: stm32: add support for disabling automatic retransmissions
Add support for disabling automatic retransmission of CAN frames
(similar to CAN "one-shot" mode in the Linux kernel).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-17 21:09:17 -05:00