Pin controller address is the same for all member of the
GEN3 SoC Series, but pinmux configuration is SoC specific.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Renesas R-Car series contains a PFC (Pin Function Controller).
This module consists of registers for selecting the function of
the multiplexed pins and controls the pull-up resistor on each pin.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Remove the unused base binding for CAN bus devices (as in devices
present on a CAN bus). This binding should have been removed in
2269408572
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix the interrupt setting in the fvp_baser_aemv8r dts:
- The correct interrupt number is 5, not 0.
- The interrupt priority and type are swapped.
This patch also enables interrupt driven mode for this platform as this
is the ideal setting for a Fast Models based platform.
Issue-ID: SCM-4037
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com>
Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96
dts/bindings/timer/riscv,machine-timer must have compatible name
riscv,machine-timer. nuclei,machine-timer is wrong, correct it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This PR adds the different handling of temperature sensor for the
STM32L5 soc. In this soc, there are some calibration settings which
need to be applied for temperature conversion.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
The dts binding general rules document states that the property
description should explain why the default value was selected
(e.g. "default is the value at power-on").
See comment in #41143
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add fragment:
io-channel-cells:
- input
to binding of the "ite,it8xxx2-adc" and "zephyr,adc-emul" compatible.
It is necessary to use io-channels property.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
The leon3 SoCs were missing definitions of the CPU node. This node is
now required for PM, so that power states can be defined.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Better setting a default value there so DT_PROP() will return something
relevant whether the property is set or not.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
HSE clock frequency value depends on target.
It can't be defaulted.
Remove this property to ensure it is set properly for each target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Kconfig options will anyway enable/disable the driver relevantly.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Assign unique memory-region attribute values for both OCM
memory areas so that the lower region starting at address 0
is identified as OCM_LOW, while the alternate location for
the OCM memory is identified as OCM_HIGH.
The updated linker command file will use those identifiers
for OCM section mapping based on which of the two OCM areas
is marked as 'chosen' at the board level.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
YAML description file for the On-Chip Memory of the Xilinx
Zynq-7000, DT identifier "xlnx,zynq-ocm".
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The spi-bus-width property provides information if the target system
has all SIO[0123] pins connected to NOR flash memory.
It must be equal to 4 to enable QSPI 4 IO operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'flash-id' property defines the number of QSPI's dedicated GPIO
bank (and flash ID), which will be used to communicate with flash
memory.
For example, on stm32h7xx it is possible to use 'quadspi_bk1_*' and
'quadspi_bk2_*' set of pins, so one may need to select between them
when required.
By default - pins from 'quadspi_bk1_*' bank are used, so the
'flash-id = <2>;' property, when your use case (e.g. PCB design)
requires it, forces usage of 'quadspi_bk2_*' pins.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Now in Zephyr only stm32f7 processors have by default provided support
for QSPI IP block.
The same IP block is also available in stm32h7 (with different offsets),
so proper DTS description shall be provided as well for it.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Convert the CAN loopback driver from being configured via Kconfig to
multi-instance configured via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The syscall_perf test cannot be built successfully due to region RAM
overflow on qemu_riscv32_xip and hifive1_revb. The dtim is only 16KB,
To reduce the main stack size to make it can be built successfully.
Base on the spec(fe310-g002-manual-v1p1.pdf), the size of itim should
be 8KB. Modify the definition in its DTS file.
And it also fix some of the gcc warning when testing it by twister.
This PR partially fixes#41399.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The vnd,gpio-device compatible is now used by the test GPIO driver
(CONFIG_GPIO_TEST) introduced in #41387. This means that we can't define
new devices with this compatible when CONFIG_GPIO=y.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
