Replace the enum for load modes for the iCE40 with a boolean flag,
as there are only two options:
- SPI: default, which should be used whenever possible
- GPIO bitbang: workarorund, in case a low-end microcontroller is used
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This will help distinguish 64 and 32-bit platforms by tooling, following
the pattern visible in e.g. RISC-V.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Those dtsi are a base for a range of 32-bit platforms. Setting this
compatible makes it easier to distinguish all 32-bit x86 platforms.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
y
atom.dtsi enforces "intel,x86", but it doesn't help us discern if the
platform is 32 or 64-bit. We do that for example in RISC-V and it's
useful from the tooling perspective.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Align the shared memories with the memory.h layout.
Reorder nodes to show memory related nodes together.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This bus type was originally created for what's today the ipc.c HCI driver.
Since this type hasn't yet been synced with BlueZ, rename it for
consistency, however leave the old define to not break backwards
compatibility with existing DT bindings (there are several more that use
"ipm" than ipc.c).
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The authoritative source of these values is BlueZ:
https://git.kernel.org/pub/scm/bluetooth/bluez.git/tree/lib/hci.h#n38
Update our values with the above. The IPM definiton doesn't exist in
BlueZ, but should be added there to make sure we don't get out of sync
again.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Remove CONFIG_MMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the mmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
mmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove CONFIG_SDMMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the sdmmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
sdmmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Define the "clocks" property, for the flash "st,stm32h7-flash-controller"
node, only for the stm32H7 dual-core devices
which have the RCC bit 8 present in their RCC AHB3 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the global power domain entry. This domain is not memory-mapped
but controlled using NRFS services.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`
Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The nrf7000, nrf7001 and nrf7002 expose a coex hardware interface
which is independent from the wifi/control interface (spi and
control pins)
These interfaces where previously combined into a single model. This
is incompatible with the actual usage of the interfaces where one
core may interact only with the coex interface, and another with the
wifi/control interface.
This commit moves the coex interface, commonly described in
"nordic,nrf70-coex.yaml", out of the wifi/control models
"nrf700<variant>-<bus>.yaml" to its own models
"nrf700<variant>-coex.yaml"
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
- Modify the macro in source code AGT to get the right data from
device tree
- Modify name of agt node
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Extended UICR will not be used as its configurations will be merged
with the UICR registers in NVR.
Memory maps changes are needed to align with pre compiled
firmware.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This commit fixes minor copyright issues and corrects the compatible of
gpio-stepper with the vendor name as zephyr
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Added NXP IRTC Driver support and binding.
This driver is expected for users needing
Time Date info in their application.
The driver additionally has an alarm mode that
can be enabled to fire an intterupt when the time
and alarm values match.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
These properties should eventually be removed from this binding as they
have been introduced to control soc specific clock trees and don't
correlate to anything in the IP, but for now just make them not required
and remove them from DT for SOCs that don't even use them.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove the "required: true" attribute from the STM32 DMAMUX binding.
This is required for STM32WB0 series where the DMAMUX has no interrupt line
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
PR #79683 missed a few nodes introduced while it was under review.
Replace the remaining raw values with STM32_CLOCK in WB0 DTSI files.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Additional IO ports (6,7 and 8) are availble on the r7fa6m4af3cfb
variant of the RA6M4 Microcontroller.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
The CSI is an NXP IP and the driver has been very much changed
by NXP, so add NXP copyright to it.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The peer remote device "source_dev" can be retrieved from the
remote-endpoint-label. Direct reference via phandle is not needed.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
