The pinsN group name can be a confusing in some circumstances, so change
it to groupN. Some platforms (e.g. nrf or gd32) are already using
groupN. Documentation and API tests have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
So far driver was using SENSE mechanism for all or none edge
interrupts. This was not convenient since in some modules may
require IN event to be used and other did not. Converting it to
use a mask specified in the device tree. Pins indicated in the
mask will use sensing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a new DT property named "pixel-group-size" that allows users to
configure the driver to refresh the matrix by illuminating multiple
LEDs in particular rows simultaneously. This way the maximum possible
brightness of the LEDs can be increased (as they can be lit longer)
and the timer interrupt handler is executed less frequently, what
results in decreased CPU load, but more GPIOTE/PPI channels needs to
be allocated if the PWM peripheral cannot be used. Thus, it is left
to users to select the configuration that suits them best.
Update definitions of both the bbc_microbit boards with this new
property, using the maximum available group size (to achieve maximum
possible brightness). For v2, no new resources are used (only all
channels in the already used PWM peripheral are now utilized).
For v1, two more GPIOTE and PPI channels are allocated.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Note: on stm32h7 not all product lines support this configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
- Supporting multiple instances of ivShMem virtual devices.
- Introduces DT based configuration for ivShMem devices.
- Add DTS overlay file to test new multiple ivshmem instance capability.
- Enable BDF unspecified device initialization.
(limited to one instance. An improved version of pcie_bdf_lookup()
will come soon that fixes this limitation)
- Make PCIE DTS file macros available for a proper ivshmem device
properties parsing.
Sample for dts file:
pcie0 {
label = "PCIE_0";
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
ranges;
ivshmem0: ivshmem@800 {
compatible = "qemu,ivshmem";
reg = <PCIE_BDF_NONE PCIE_ID(0x1af4,0x1110)>;
label = "IVSHMEM";
status = "okay";
};
};
Signed-off-by: Michael Schmidt <michael1.schmidt@intel.com>
Modifying configuration to enable with gd32vf103
- Add usart definition to devicetree.
- Define USART_STAT as alias of USART_STAT0 if not defined it.
- Enable USART if SOC_SERIES_RISCV_GIGADEVICE_GD32VF103.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
As Nordic SPI, I2C and UART buses can act as both slave and master,
these nodes can have different compatible properties, and are annotated
with a comment, instead of a compatible property. This forces boards to
put compatible properties in their definitions, which is unnecessary
boilerplate for most boards, as most boards acts as masters on these
buses.
Set master mode by default for these buses, to reduce boilerplate and
potential errors in board definitions. Boards that need to act as slave
nodes will just continue to override the compatible properties.
Likewise, existing boards that override this compatible property with a
master binding will not be affected by this change.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
The stm32u5 device has a single iwdg node entry and label
without any need for interrupt. Even if it exists the irq entry
is not required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implemented driver for the simcom sim7080 modem.
This driver features Socket offloading, TCP, UDP, DNS,
SMS, GPS and FTP.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Remove the requirement for specifying #address-cells and #size-cells
properties for CAN controller devicetree nodes.
CAN controllers do not have a common concept of devicetree child nodes
and thus have no need for these properties. This is in line with
upstream Linux kernel devicetree bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NPCX series used npcx-lvol-ctrl-map to record the GPIO & low voltage
control register map. However, GPIOE3 was configured as GPIOE6, which
is a non-existed pin. This commit fixes the GPIOE3 low voltage control
map.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Move odr and range properties for both accelerometer and gyro
from Kconfigs to Device Tree.
Fixes#41117
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Fix the yaml dts multi-line property description in the following
(expected) way:
description: |
PUT_TEXT_HERE
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Adding support for the TI TMP108 temperature sensor. This includes
over/under temp interrupt support as well as one shot, continuous
conversion and power down modes.
Signed-off-by: Jimmy Johnson <catch22@fastmail.net>
By enabling SMP option plus the APPCPU, also
completes the SMP port by adding the esp32
specific arch_sched_ipi() function
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a display driver and the corresponding devicetree binding for a LED
matrix with rows and columns driven by nRF SoCs GPIOs. Such matrix can
be found, for example, in the BBC micro:bit boards.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
When building for an STM32K010xB MCU, there is a deprecated properties
warning, which should be fixed by this PR.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
Everything I can find as a reference says that the LP-SRAM block on
these devices is 64kb, and direct experimentation with cAVS 1.5 and
2.5 agrees. Access to areas beyond 64k hangs the DSP (it should cause
a PIF fault I guess, but the exception never gets trapped, that's
probably a different problem).
Fix this in devicetree to reflect what actually works. It's not clear
where the 128k values came from; if they're not typos we can correct
that when we find better docs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Create an explicit ina230 driver which is supposed to
work with 230 and 231 variants. While at it switch
to i2c_dt_spec helpers and change device-tree node
names to use - instead of _ in order to follow
convention.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Create a common properties file that will be included by all bindings
(as i2c and spi) handled by lps22hh driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
PSL_IN pin select register is Vsby power-up reset. When the other
core-domain-reset reset the chip, PSL_IN3/4 don't set to GPIO. This
commit adds PSL_IN3/4 to the pin select list in NPCX devicetree. So
these pins can be set to GPIO when the other core-domain-reset.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
GPT base address in the devicetree for the RT11xx SOC series was
incorrect, this commit fixes it
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for the 8 channels TCA9548A I2C mux.
Added a new binding ti,tca9548a binding inheriting
properties from ti,tca954x-base and defining its own compatibles fields.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add an optional "reset-gpios" phandle-array
field to the driver common yaml.
The reset GPIO channel and pin can be defined
in device tree as a node property.
The driver then deassert the reset signal at mux
initialization if a "reset-gpios" has been specified.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Prepare the driver to upcoming support of more mux references.
Rename all TCA9546A related files to TCA954x.
Keep ti,tca9546a and ti,tca9546a-channel compatible
for backward compatibility reasons.
New tca954x-base binding embedding common properties,
tca9546a binding inherits from it and define its own compatibles fields.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Include the mem-region bindings for the stm32 ccm nodes and set the name
in the current dtsi files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
