Enable pinctrl for ethernet mcux driver, and update kinetis DTS node to
include labelling for PTP node, to enable driver to access pinctrl
properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
kinetis pinctrl driver had swapped values for slew rate
(fast slew rate should set bit to zero). Fix slew rate values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Move the SX oscillator control pins to a regulator node
- Create a board level compatible for the RF switch
- Use gpio_dt_spec to simplify board pins.c (now rf.c)
- Cleanup include list
For reference:
https://downloads.rakwireless.com/
LoRa/RAK811/Hardware_Specification/RAK811_HF_Schematics.pdf
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add build time optional PINCTRL support to common PWM driver
for Microchip XEC MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for MEC172x series to Microchip XEC PWM driver.
Standardize device tree properties for both SoC families.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add the Vref reference voltage in the DTS, so that the adc driver
can retrieve the value for conversion.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The datasheet for both sam4s/same70 specifies that the NRST pin
is an input after reset, used as a user reset.
Add the user-nrst property to match the default.
Fixes#43306
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Adds 'swj-cfg' property to the F1 pinctrl. It is an optional
property that allows to control Serial Wire JTAG
configuration.
Different configurations allow to free certain IO
pins that can be used in remap or standalone.
That replaces previously used Kconfig approach.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This contains accessor macros for getting the maximum bitrate supported
by a CAN controller/transceiver combination.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add generic devicetree bindings for simple CAN transceivers.
Always-on CAN transceivers are considered passive and just provide a
maximum supported bitrate.
Active CAN controllers can typically be controlled by the MCU via either
SPI, I2C, or GPIO. Common GPIO controlled CAN transceivers provide
either a stand-by or an enable pin (or both) for controlling the state
of the CAN transceiver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the new pinctrl API to the nRF PWM driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QDEC driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the DMIC driver that handles
the nRF PDM peripheral. Update code of the driver and the related
devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF I2S driver. Update code
of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Bindings for the Xilinx Processor System GPIO controller, both for the
parent controller device as well as the GPIO pin bank child devices.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add the parent controller device node plus the child nodes for all
GPIO pin banks managed by the GPIO controller to the device trees
of the Zynq-7000 and ZynqMP SoCs.
Device base addresses, IRQ lines, number of banks, number of pins
per bank and bank descriptions taken from the Zynq-7000 TRM (Xilinx
document ID ug585), the Zynq UltraScale+ TRM (Xilinx document ID
ug1085) and the Zynq UltraScale+ Devices Register Reference (Xilinx
document ID ug1087, web-based document).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
add dtsi settings for rt series
dtsi use gpr to replace pinmux
nxp iomuxc has gpr which has more settings than mux and io settings
current solution is to export gpr separately and access then directly
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add dts binding for rt1xxx pinctrl driver settings. A binding file is
present for the pinctrl node itself, and for the pinctrl child node that
defines all pinmux options
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce ADC properties which indicated if the ADC instances have
dedicated channels for the internal temperature sensor or voltage
reference.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Don't set AFIOEN when enabling IO port clock.
The bit is set upon requirement within pinctrl
or pinmux
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
RT11xx USB PLLs source from 24MHz XTAL oscillator. Add this oscillator
as a clock source for the usb dts entries for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This macro expands to DT_STRING_TOKEN if property exists, otherwise
falls back to default value.
Helpful when a non-required enum binding doesn't mention a default
value, but a default value makes sense to be set in the code.
Including DT_INST_STRING_TOKEN_OR and test code.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
rename IMX_CCM_UART_CLK to IMX_CCM_UART4_CLK and
IMX_CCM_UART2_CLK a53 dtsi.
This was missed in a previsous patch set.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for the new pinctrl API to the I2C drivers that handle
the nRF TWI and TWIM peripherals. Update code of the drivers and
related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
