Call entropy APIs to use TRNG peripheral on STM32WB0x devices for BLE
purposes.
Enable RNG node on Nucleo-WB0x boards.
Remove RNG initialization as it's done in the entropy driver.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
On Cortex-M33 the access to peripheral registers doesn't act as a data
synchronization barrier for memory accesses to normal memory. So before
triggering any TASKS for cache operations we need to make sure the core
doesn't have any pending memory transactions.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
When reception is restarted (STARTRX after ENDRX but no STOPRX) it is
possible that FRAMETIMEOUT countdown counter will not be started by
the first received byte if byte was already being transmitted when
STARTRX was called. If that is the only byte then it is expected that
timeout will be triggered but since FRAMETIMEOUT counter is not started
there is no FRAMETIMEOUT event which has short to STOPRX. This
situation will happen in case short buffers are used (< 5 bytes)
because then short ENDRX_STARTRX is not used then.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Converting absolute system ticks to RTC ticks is simple. It needs to be
multiplied by CYC_PER_TICK (which by default is 1). Complex algorithm
was used when driver was not tracking current 64 bit tick and function
was returning uint32_t.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
When both NRF_CLOCK_HAS_XO_TUNE and NRF_CLOCK_HAS_PLL evaluate to 0,
one break statement can end up not associated with any case and become
dead code. Refactor a bit the related switch to avoid such situation.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add reference counting in nrf_qspi_nor_xip_enable() so that XIP is
kept enabled as long as there is at least one user that needs it
(boot time enabling done with CONFIG_NORDIC_QSPI_NOR_XIP also counts).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Configure the active discharge feature for both the BUCK and LDO/LDSW
blocks through the appropriate registers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Some macros haven't been properly renamed in previous commits.
Fixes the wrong names that caused compilation errors.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This driver uses the NRF_CLOCK_HAS_HFCLKAUDIO symbol that is defined
in <hal/nrf_clock.h>, so it should explicitly include that header,
not count on this inclusion being done by some other header, like
<zephyr/drivers/clock_control/nrf_clock_control.h>.
Extend also the build assertion that checks if the audio clock can
be used so that now it ensures that the above symbol is defined
(to prevent the driver from silently discarding the audio clock
configured as the clock source).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
If gpio-reserved-ranges to reserve some pins which used by other CPU
Core's OS, we could only handle usable pins owned by current CPU
Core in interrupt handler.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
If the platform uses SCMI pinctrl driver, pinctrl regitster can't accessed
by CPU Core directly, and currently SCMI pinctrl driver has no API to read
back the register value, so use default pad config value for GPIO pad
configuration, and in theory we could use a fixed pad config value in this
driver as each new GPIO configuration has no relation with previous
configuration.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Increased the default number of TX and RX buffer descriptors from 4 to
16. Since the current default buffer size (CONFIG_NET_BUF_DATA_SIZE) is
128, increasing the number of RX buffers is needed to be able to receive
at least one frame of a maximum size split between multiple buffers.
The default number of TX buffers was increased to match the number of RX
buffers and to be able to transmit large frames with many fragments.
Added build-time configuration validation to ensure that the combined
size of all RX buffers is sufficient to receive a maximum-sized Ethernet
frame.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
DMA copies frames which cannot fit into a single buffer into
multiple receive buffers. Updated the receiving code to combine
these buffers into a net_pkt with multiple fragments.
This allows the driver to handle larger Ethernet frames that
span across multiple DMA buffers.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Always reading from descriptor with index 0 could cause processing
of the buffers in a different order than they were received. Fixed by
reading from the next unprocessed position in the ring of descriptors
instead.
Fixed unused variable warnings.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Two DMA channels are assigned to AES channels A and B respectively.
Each channel A/B has an interface to control the conditions that will
generate requests on the related DMA channel: trigger condition,
R/W address, and DMA done action.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The CYW43xxx for Infineon Controllers stops after the first LauncRAM
command. Newer Controllers like the CYW5557x update the firmware in
multiple stages, which is supported by this commit.
Signed-off-by: Matthias Ringwald <matthias@ringwald.ch>
make sure that autonegotiation is restarted, after
changing the speeds. Also make sure to only write
the changed registers, as mdio is pretty slow.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove phy related configs from eth config.
phy related configs chould go directly into the phy.
Most ethernet drivers didn't support the now removed
functions yet. Users should instead use `phy_configure_link()`
together with the `net_eth_get_phy()` function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Newer AIROC controllers like the CYW55573 don't support changing the
baudrate in Download Mode. However, a higher baud rate can be used
directly to sent HCI Reset.
This commit adds the KConfig flag CONFIG_AIROC_DOWNLOAD_MODE to enable
the new behaviour.
Signed-off-by: Matthias Ringwald <matthias@ringwald.ch>
Prevent integer underflow when sequence->channels is 0.
Add an explicit check before calling find_msb_set().
Coverity CID: 487765
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Only include cmsis_core.h on ARM platforms, including it unconditionally
as it is now causes a build failure on all other platforms, namely x86
on the weekly build run.
Tested with:
west build -p -b up_squared/apollo_lake tests/drivers/build_all/led
(and others)
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
PG142 from AMD specifically says the uartlite IP generates a
"rising-edge sensitive interrupt" when interrupts are enabled. When
using this IP on a ZynqMP platform with
CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get
configured correctly to detect these interrupts. Update driver to heed
the flags set by the interrupts property in the device tree.
Signed-off-by: Michael Estes <michael.estes@byteserv.io>
Fix channel ID check in dac_esp32_channel_setup as it was allowing to
set up a channel with ID greater than the number of channels.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The IRER registers are write-only and clear the enable bit for the
provided interrupt. Use a direct write instead of a read/modify/write
sequence to avoid generating a bogus read access and improve performance
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Some ADC's draw significant power while enabled, so make sure the
driver can handle ADC's that have device runtime PM enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Reset the SPI peripheral to its default state
and register values on init by setting its SWRST bit.
This is important since the driver assumes that certain
registers are at their default values.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
The sam0 SPI driver does not ensure that it clears the 32-bit extension
option during init. The 32-bit extension option, which comprises of a field
in the CTRLC register and the LENGTH register enables better bus
utilization by allowing 32-bit writes to the SPI DATA register
(as opposed to the usual 8-bit writes). The driver breaks down if this
option is enabled by causing each intended byte of output to become
four bytes. We fix this by explicitly disabling the 32-bit extension
option in init.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Change nxp_imx_mu_send() to return a negative errno value
on error.
The fsl_mu function MU_TriggerInterrupts() returns either
kStatus_Success or kStatus_Fail, which have the value 0
or 1, respectively. kStatus_Fail should not be returned
to the upper levels, which expect negative values for
errors, so add a check for the return value of
MU_TriggerInterrupts() and return an errno value on error.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The mode is activated by the CONFIG_MODBUS_NONCOMPLIANT_SERIAL_MODE option
and allows any stop-bit setting for the serial port.
Signed-off-by: Maksim Salau <msalau@iotecha.com>
To determine whether device runtime PM is enabled on a device, use
`pm_device_runtime_is_enabled`. This results in the same behaviour when
`CONFIG_PM_DEVICE_RUNTIME=n`, but properly controls the clocks on a
per-instance basis when `CONFIG_PM_DEVICE_RUNTIME=y`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Counting module, Capture block (measure input signal period/time) and
Compare block (to generate time expiry, output waveform like PWM).
Add a support for counter driver with alarm and counter top functions.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
IDLEOUT presence in PWM means that there are 3 sources from which
PWM pin can be driven:
- GPIO setting when PWM peripheral is disabled.
- IDLEOUT setting when PWM is enabled.
- PWM Sequence when it is in use.
IDLEOUT setting cannot be changed after enabling PWM so it is
configured to the initial state of the pin. It means that if duty
cycle is 100%, GPIO output is set to 1 but initial pin state was 0
(IDLEOUT setting) there will be a glitch between disabling a PWM
sequence and disabling a PWM peripheral.
By default, PWM driver tries to disable PWM peripheral if all channels
are 0% or 100% duty cycle to safe power. When IDLEOUT feature is
present there will be a short glitch on channels with 100% duty cycle.
In order to avoid that CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 option is
added (enabled by default). When option is enabled 100% duty cycle
is achieved by PWM sequence and not by driving a GPIO pin. It will
consume more power in cases where all channels are 0% or 100% with
at least one channel set to 100% duty cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
