When a request is performed on a single accelerometer axis
(e.g. SENSOR_CHAN_ACCEL_X) the driver must return a single
scalar q31 data.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In a IMU there might be multiple concurrent asynchronous requests
active at the same time. Increase the size of the RTIO queues.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add support for the SPI module on TI’s MSPM0 MCUs.
The driver supports master mode transfers with configurable
frame size (4–16 bits), clock polarity/phase, bit order.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
Merge the separate BL70X and BL70XL HCI drivers (hci_bflb_bl70x.c,
hci_bflb_bl70xl.c) into a single hci_bflb.c. Both SoCs share the
same on-chip HCI interface; platform differences (controller API
names, includes, RF calibration) are resolved via macros in a
single #if/#elif block at the top of the file.
Add BL70XL Kconfig (silicon revision, BLE variant selection) and
update depends lines to use the unified DT_HAS_BFLB_BT_HCI_ENABLED
combined with the SoC series.
Signed-off-by: William Markezana <william.markezana@gmail.com>
move net_eth_mac_load into iface init, that way we don't
need to save the mac address in the data struct.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Expose mode 3 (ODR-triggered) in gyro_set_mode and gyro_get_mode for
lsm6dsv320x, lsm6dsv80x, and ism6hg256x so gyro mode matches accel mode
as required by datasheet section 6.1.5.
Fixes#106389
Signed-off-by: Nancy Sangani <9d.24.nancy.sangani@gmail.com>
Add disabling of write protection also on read access to bbram for h7rsx
controllers.
On this controller family, reading the backup register will return 0 when
write protection is enabled.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Fix two issues in the NXP HCI firmware upload code:
1. In fw_upload_wait_length(), the length complement was incorrectly
read from the same buffer offset as the length field. It should be
read from offset 2 to properly validate the length field.
2. In fw_upload_write_hdr_and_payload(), replace the call to
fw_upload_send_ack() with a direct call to fw_upload_write_data()
to send the V1_REQUEST_ACK. This ensures the ACK is sent using the
correct write function.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
A similar fix was implemented for TWIM driver at 9974bb043f.
The bus recovery code at nrfx driver reconfigures SCL/SDA pins (namelly
sets pull-up resistors) so we need to restore the configuration to the
specified state of pinctrl after the recovery operation.
Signed-off-by: Lluis Miquel Martinez Campos <lluiscampos@proton.me>
After sys_reboot or debugger reset on nRF54LM20, USB controller fails to
initialize because the VREGUSB peripheral retains state across warm
resets. Two issues are addressed:
1. Stale VBUS_DETECTED/VBUS_REMOVED events from the previous boot
remain set in the event registers. When interrupts are enabled
without clearing them first, the ISR fires immediately with
potentially wrong event type (VBUS_REMOVED can overwrite
VBUS_DETECTED in the handler).
2. When USB cable stays connected across a reboot, no new
VBUS_DETECTED edge occurs because the peripheral was never
stopped. The regulator callback never fires, so the wrapper
never posts NRF_USBHS_PHY_READY, and usbhs_enable_core()
blocks indefinitely or times out.
Fix by clearing stale events before enabling interrupts, and by
reading the undocumented STATUS register (base + 0x400, bit 2) after
TASK_START to detect VBUS-already-present and synthesize the
REGULATOR_VOLTAGE_DETECTED callback. This matches the approach used
in the original inline vendor quirks added in commit 66b938f93a
("drivers: udc_dwc2: Add nRF54LM20A vendor quirks")
before the refactoring to a separate regulator driver.
Signed-off-by: Aleksander Strzebonski <aleksander.strzebonski@nordicsemi.no>
Add support for new pixel formats recently added in the driver header.
These formats are supported by the lcdif controller on mimxrt700_evk:
- PIXEL_FORMAT_RGB_888: 24-bit RGB format with 8 bits per component
- PIXEL_FORMAT_BGR_888: 24-bit BGR format with 8 bits per component
- PIXEL_FORMAT_ABGR_8888: 32-bit ABGR with alpha channel
- PIXEL_FORMAT_RGBA_8888: 32-bit RGBA with alpha channel
- PIXEL_FORMAT_BGRA_8888: 32-bit BGRA with alpha channel
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Improve the coordinate and address alignment logic in the CO5300
display driver. The driver now properly aligns the framebuffer
address according to the addr_align property from device tree,
in addition to ensuring coordinates are even values.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
The __HAL_RCC_PKA_IS_CLK_ENABLED macro doesn't exist in HAL2. Replace it
with LL calls that exist in both versions.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Updated async mode to read the first byte manually and the
remaining bytes using dma as buffer overflow was happening
for rx enable with 1 byte.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Adds a dummy define to prevent compilation issue when HSE is not enabled,
and STM32_HSE_FREQ is set to 0.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
To access the OTP area on STM32C5, the instruction cache needs to be
disabled to prevent a bus fault.
Do it for the OTP driver, as well as the temperature and Vref sensor.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Add #define of BREG for infineon edge soc family
- Add #include <stdlib.h> to support "abs" call for edge family soc
- Above #include is not required in the rtc driver for psc3m5 support
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Align all sensor drivers that are using stmemsc (STdC) HAL i/f
to new APIs of stmemsc v2.13.1
Requires https://github.com/zephyrproject-rtos/hal_st/pull/33
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Extends ADP5360 Regulator API support to the existing
ADP5360 Buck and Buck Boost Regulator.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements fuel gauge subsystem for ADP5360 MFD driver.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Adds Charger subsystem support for the ADP5360 MFD device.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements I2C communication used by drivers under this parent device,
interrupt support, supervisory data configuration,
and power management subsystem API.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
The boards and shield using W5500 chip on latest release (v4.4)
require higher stack size to function
Signed-off-by: Krisztian Szilvasi <krisztian@atym.io>
In target mode, a STOP condition following a read transaction is
signalled via the idle interrupt. Invoke tcbs->stop() in this path
so the application receives the stop callback for read transactions.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
During a write-read combined transfer (e.g., register read), the write
phase completes and msg_read() calls enable_transfer_interrupts() which
re-enables ITBUFEN. However, the TXE flag from the write phase is still
asserted (hardware only clears it on DR write or ADDR clear). The event
ISR sees TXE=1 but is_write is now false, so no handler matches and the
ISR returns without clearing TXE — causing an infinite interrupt loop.
Fix this with two changes:
1. In i2c_stm32_event(), catch TXE active during a read transfer and
disable ITBUFEN to quench the stale TXE interrupt source.
2. In handle_addr(), re-enable ITBUFEN after clearing ADDR. The ADDR
clear implicitly clears TXE, so re-enabling ITBUFEN at this point
is safe and ensures RXNE interrupts work correctly for the read
phase.
Signed-off-by: Gowtham Palanichamy <gowtham.palanichamy@rapyuta-robotics.com>
When BTF fires after the last byte is transmitted, it calls handle_txe()
with data->current.len already at 0. The else branch generates a stop
condition and signals completion via k_sem_give, but does not disable
ITBUFEN first. Since TXE is level-triggered and remains asserted until
DR is written, the event ISR can re-fire on the stale TXE flag.
Add LL_I2C_DisableIT_BUF() at the top of the else branch as a defensive
measure so the level-triggered TXE cannot re-enter the ISR after the
transfer is logically complete.
Signed-off-by: Gowtham Palanichamy <gowtham.palanichamy@rapyuta-robotics.com>
After an I2C error (NACK, ARLO, BERR), the error handler jumps to the
end: label which calls i2c_stm32_controller_mode_end() (k_sem_give)
without first disabling transfer interrupts. If ITBUFEN (CR2 bit 10) is
still asserted and TXE is high, the event ISR re-fires immediately after
the error ISR returns, creating an infinite interrupt storm that
hard-freezes the CPU.
Disable all transfer interrupts (ITEVTEN, ITERREN, ITBUFEN) before
calling i2c_stm32_controller_mode_end() so the ISR cannot re-enter on a
stale TXE flag. When CONFIG_I2C_TARGET is enabled, only do this for the
controller path to avoid interfering with target mode operation.
Signed-off-by: Gowtham Palanichamy <gowtham.palanichamy@rapyuta-robotics.com>
Updated PCR and GIRQ properties to use new macros.
Updated symcr and romapi node for mec174x/5x/165xb
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Apply three documented SX1261/62 silicon errata from DS_SX1261-2_V1.2:
- IQ Polarity (chapter 15.4): after every SetPacketParams command,
manually fix bit 2 of REG_IQ_POLARITY to match the requested IQ
inversion setting. Without this, inverted-IQ packets (used by
LoRaWAN downlinks) may be silently corrupted.
- TX Modulation Quality at 500 kHz (chapter 15.1): clear bit 2 of
REG_TX_MODULATION when using 500 kHz bandwidth, set it otherwise.
Without this, 500 kHz transmissions have degraded modulation quality.
- Register Retention: add REG_RX_GAIN and REG_TX_MODULATION to the
chip's internal retention list so their values survive warm-start
sleep cycles, matching the upstream Semtech reference driver.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The SX126x requires a minimum preamble length of 12 symbols when using
spreading factors 5 or 6 (DS.SX1261-2.W.APP, Rev 2.2, section 6.1.1).
Shorter preambles at these spreading factors can cause failed detection
on the receiver side.
Clamp the stored preamble length after configuration so that all TX, RX,
and airtime paths use the corrected value.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
test_cw() only checked that the radio was idle before starting a
continuous-wave transmission. It never moved the driver out of the rest
state, so another TX or RX operation could start while the CW test was
still active.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The native SX126x driver accepted unsupported LoRa bandwidth enums and
silently mapped them to 125 kHz. That could leave the modem running with
a different configuration than the caller requested, and it also skewed
airtime calculations.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When setting SFLP game gbias the accel/gyro data rate must be temporarily
changed and then restored back to original values. But in the process the
saved rates got mistakenly corrupted.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
If gpio level gets immediately at high level after sensor is started,
then call interrupt stream handler in order to avoid losing it. As a
side effect no data would be ever read.
Co-authored-by:Brenden Adamczak <cerebralasylum1@gmail.com>
Signed-off-by: Brenden Adamczak <cerebralasylum1@gmail.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add handling of missing NRF_BICR LFOSC modes MODE_PIERCE and MODE_PIXO
and filter out unsupported modes with preprocessor macros provided by
nrfx.
Signed-off-by: Jari Tervonen <jari.tervonen@nordicsemi.no>
native_tap only queued TX timestamp callbacks for gPTP packets, which
left PTP SO_TIMESTAMPING socket traffic without TX timestamps.
Add host-clock packet timestamp updates in native_tap TX/RX paths, queue
TX timestamp callbacks when net_pkt_is_tx_timestamping() is set (while
preserving gPTP behavior without double-queueing), and propagate
SO_TIMESTAMPING TX/RX flags for AF_PACKET packets in net_context.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
RM0481 Rev 4 documents the Ethernet PTP timestamp clock as a dedicated
reference clock (`clk_ptp_ref_i`), not the `eth_hclk` bus clock.
Table 115 ("Kernel clock distribution overview", p. 470/3154) lists
`ETH (ptp)` on `pll1_q_ck`, and the IEEE 1588 section states that the
64-bit PTP time is updated from `clk_ptp_ref_i`.
Add an explicit `mac-clk-ptp` clock for STM32H5 sourced from
`STM32_SRC_PLL1_Q`, use that clock rate for PTP addend programming.
Because this change introduces source-clock configuration for STM32
Ethernet clocks, update the STM32H7 DWMAC path as well: use
`clock_control_configure()` for source clocks such as `eth-ker`, while
keeping `clock_control_on()` for gated clocks.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
1. Remove the NRF_PLATFORM_HALTIUM and NRF_PLATFORM_LUMOS Kconfig
symbols and eliminate all "haltium"/"lumos" naming from the zephyr
directory.
2. The shared haltium_power.c/h and haltium_pm_s2ram.c/h files from
soc/nordic/common/ are duplicated into the per-SoC-series directories
(nrf54h/ and nrf92/) as soc_power.c/h and soc_pm_s2ram.c/h. The
corresponding build rules are moved from common/CMakeLists.txt to the
per-series CMakeLists.txt files.
3. Kconfig guards that relied on the platform symbols are replaced with
individual hardware feature checks derived from nrfx/MDK:
- select NRFX_POWER if !NRF_PLATFORM_HALTIUM -> if HAS_HW_NRF_POWER
- CLOCK_CONTROL default ... !NRF_PLATFORM_HALTIUM -> HAS_HW_NRF_CLOCK
- depends on NRF_PLATFORM_LUMOS -> SOC_SERIES_NRF54L||SOC_SERIES_NRF71
4. C preprocessor guards using CONFIG_NRF_PLATFORM_HALTIUM are replaced
with explicit SoC series checks (CONFIG_SOC_SERIES_NRF54H ||
CONFIG_SOC_SERIES_NRF92).
5. The sysbuild option NRF_HALTIUM_GENERATE_UICR is renamed to
NRF_GENERATE_UICR.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
