drivers: clock_control: update mcux_lpc_syscon_clock.c drivers
add more flexcomm instances clock support to adapt rt700 instances number add xspi clock support Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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1aa49ae28f
commit
47cc069cb9
2 changed files with 80 additions and 5 deletions
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@ -25,7 +25,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
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#endif /* defined(CONFIG_CAN_MCUX_MCAN) */
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#if defined(CONFIG_COUNTER_NXP_MRT)
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if ((uint32_t)sub_system == MCUX_MRT_CLK) {
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#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||\
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#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) || \
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defined(CONFIG_SOC_SERIES_MCXN)
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CLOCK_EnableClock(kCLOCK_Mrt);
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#elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
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@ -242,14 +242,65 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
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*rate = CLOCK_GetLPFlexCommClkFreq(9);
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break;
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case MCUX_FLEXCOMM10_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(10);
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break;
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case MCUX_FLEXCOMM11_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(11);
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break;
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case MCUX_FLEXCOMM12_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(12);
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break;
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case MCUX_FLEXCOMM13_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(13);
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break;
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case MCUX_FLEXCOMM17_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(17);
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break;
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case MCUX_FLEXCOMM18_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(18);
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break;
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case MCUX_FLEXCOMM19_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(19);
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break;
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case MCUX_FLEXCOMM20_CLK:
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*rate = CLOCK_GetLPFlexCommClkFreq(20);
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break;
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#endif
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/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */
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#if defined(CONFIG_SOC_SERIES_IMXRT7XX) && defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
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case MCUX_LPSPI14_CLK:
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*rate = CLOCK_GetLPSpiClkFreq(14);
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break;
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case MCUX_LPI2C15_CLK:
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*rate = CLOCK_GetLPI2cClkFreq(15);
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break;
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case MCUX_LPSPI16_CLK:
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*rate = CLOCK_GetLPSpiClkFreq(16);
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break;
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#endif
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#if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
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#if CONFIG_SOC_SERIES_MCXN
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#if defined(CONFIG_SOC_SERIES_MCXN)
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case MCUX_USDHC1_CLK:
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*rate = CLOCK_GetUsdhcClkFreq();
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break;
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#elif defined(CONFIG_SOC_SERIES_IMXRT7XX)
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case MCUX_USDHC1_CLK:
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*rate = CLOCK_GetUsdhcClkFreq(0);
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break;
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case MCUX_USDHC2_CLK:
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*rate = CLOCK_GetUsdhcClkFreq(1);
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break;
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#else
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case MCUX_USDHC1_CLK:
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*rate = CLOCK_GetSdioClkFreq(0);
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@ -455,6 +506,18 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
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*rate = CLOCK_GetLpi2cClkFreq(3);
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break;
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#endif /* defined(CONFIG_I2C_MCUX_LPI2C) */
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#if defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED)
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case MCUX_XSPI0_CLK:
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*rate = CLOCK_GetXspiClkFreq(0);
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break;
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case MCUX_XSPI1_CLK:
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*rate = CLOCK_GetXspiClkFreq(1);
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break;
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case MCUX_XSPI2_CLK:
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*rate = CLOCK_GetXspiClkFreq(2);
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break;
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#endif /* defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) */
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}
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return 0;
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@ -40,9 +40,16 @@
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#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK
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#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F)
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#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10)
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#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00)
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#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01)
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#define MCUX_FLEXCOMM17_CLK MCUX_LPC_CLK_ID(0x01, 0x11)
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#define MCUX_FLEXCOMM18_CLK MCUX_LPC_CLK_ID(0x01, 0x12)
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#define MCUX_FLEXCOMM19_CLK MCUX_LPC_CLK_ID(0x01, 0x13)
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#define MCUX_FLEXCOMM20_CLK MCUX_LPC_CLK_ID(0x01, 0x14)
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/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */
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#define MCUX_LPSPI14_CLK MCUX_LPC_CLK_ID(0x01, 0x24)
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#define MCUX_LPI2C15_CLK MCUX_LPC_CLK_ID(0x01, 0x25)
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#define MCUX_LPSPI16_CLK MCUX_LPC_CLK_ID(0x01, 0x26)
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#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00)
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#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01)
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#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00)
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@ -103,4 +110,9 @@
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#define MCUX_LPI2C2_CLK MCUX_LPC_CLK_ID(0x14, 0x02)
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#define MCUX_LPI2C3_CLK MCUX_LPC_CLK_ID(0x14, 0x03)
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#define MCUX_XSPI_CLK MCUX_LPC_CLK_ID(0x15, 0x00)
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#define MCUX_XSPI0_CLK MCUX_LPC_CLK_ID(0x15, 0x00)
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#define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01)
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#define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */
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