Just to get something to test for PM, via frdm_k64f board. So only this
board will get PM enabled.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
By changing the various *NET_DEVICE* macros. It is up to the device
drivers to either set a proper PM function or, if not supported or PM
disabled, to use device_pm_control_nop relevantly.
All existing macro calls are updated. Since no PM support was added so
far, device_pm_control_nop is used as the default everywhere.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert older DT_INST_ macro use in openisa drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
Convert older DT_INST_ macro use in microchip drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in atmel sam drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in sifive drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in STM32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The primary problem was that the callback was being invoked twice,
which broke the tests.
A secondary issue is that when two level tests occur consecutively the
second will fail. Instrumentation confirms that the registers are
being configured correctly, and ip indicates that the condition was
detected, but the interrupt does not occur. Tests pass as long as no
level test precedes the failing test.
It's not clear whether this is an issue with the PLIC, or the GPIO
implementation (hardware or software). As "normal" GPIO applications
appear to work we'll run with it and keep an issue open.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The Atmel DFP headers define two "component typedef styles": RFO and
NTO; where the latter makes use of bit field structs to access hardware
registers.
The default component typedef style assumed by the DFP headers (i.e.
when `COMPONENT_TYPEDEF_STYLE` is not explicitly defined) is "RFO" and
this is indeed the component typedef style used throughout the Zephyr
Atmel SAM drivers, except in the particular instance which this commit
addresses.
The use of `GMAC_TA_Type` bit field struct, which is an "NTO" style
construct, is no longer possible with the latest DFPs because
conditional compilation checks for the bit field struct definitions
were added to restrict the use of such constructs to only when the
global component typedef style is set to "NTO".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The new Atmel DFP USBHS component headers provide mode-specific
interrupt register field definitions that replace the generic
definitions (e.g. `USBHS_DEVEPTISR_RXSTPI` for a control endpoint is
now `USBHS_DEVEPTISR_CTRL_RXSTPI`).
This commit updates the Zephyr SAM USBHS driver to use the new
mode-specific interrupt register field definitions.
In addition, it maps the generic definitions to the mode-specific
definitions, as the revision A variant headers (e.g. same70a) in the
latest DFPs, at the time of writing, still provide only the generic
definitions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Convert older DT_INST_ macro use in esp32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename DT_INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 defines to something
non-DT prefixed. This way we know which defines are one's we generate
and which ones are driver created. It should be easy enough to replace
these INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 define with DTS generated
one macros once esp32 has interrupt controller support in DTS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in silab drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in cc13xx_cc26xx drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in stellaris drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds the per CPU address offset for intel_apl_adsp, so
the correct base address can be calculated under SMP.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a rather primitive driver for use with the Intra-DSP
Communication (IDC) on the DSP on certain Intel SoCs. The IDC
generates interrupts from one core to another by writing to
certain registers. This is also being utilized as
the scheduler IPI since it can interrupt other cores.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer on some Intel SoC is a timer driven
directly by external oscillator and is external to the CPU
core(s). It is not as fast as the internal core clock, but
provides a common and synchronized counter for all CPU cores
(which is useful for SMP).
This uses the RISCV timer as base as it is using 64-bit
counter.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The CAVS interrupt controller has different base addresses for
each CPU. When running under SMP, the driver needs to look at
the correct address for the CPU the ISR is running so interrupts
can be dispatched correctly. This adds a function to calculate
the correct base address. Note that each supported SoC may have
different offsets so per SoC config will need to added. Support
for intel_s1000 is added as an example.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The dw_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The cavs_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It was observed that leaving the pin type configured for i2c for SDA
and SCL results in higher power consumption during standby. So we are
resetting the pin type when bringing the i2c into low power mode, and
setting it back to the correct type when exiting low power mode.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add a dependency on the I2C resource in the TI Power module,
reconfigure the peripheral upon CPU exiting standby, and add
support for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
