Add support for the SX126x series of LoRa radios using the
LoRaMAC-Node HAL.
This driver currently makes the following assumptions:
* DIO1 is used as an interrupt line.
* There is an RF switch selecting between the TX and RX ports and
that switch is controlled by DIO2.
* There is either no TCXO or the TCXO is controlled by DIO3.
Specifically, the limitations above mean that modules that use GPIOs
to control the RF switch are currently not supported. Support for such
modules would need changes to the LoRaMAC-Node code.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add a new configuration option, LORA_SX12XX, that is shared for all of
the LoRaMAC-node-based radio drivers. By default, the appropriate
driver for the LoRa radio in the device tree is included is included
in the build.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Some boards may include an APA102 LED on an existing SPI bus. With
additional circuitry, chip select is supported where the APA102
lacks a built in CS pin.
This patch allows CS to be defined in the devicetree (through .dts
files) and utilised in the apa102.c driver if it's available. Preserving
old behaviour if no chip select is defined.
Signed-off-by: Roman Vaughan <nzsmartie@gmail.com>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The front side bus interrupt delivery feature is a somewhat obscure
part of PC history (in some sense a presaging of MSI interrupts) that
we don't use.
But it's part of the spec, works on hardware, has precedence over the
"legacy" interrupt routing feature we do use, and can be legally
enabled by firmware.
Disable at init time.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a typo in the function pointer assigned to get_parameters. It
should be flash_sam_get_parameters.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occur.
A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the
previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Right now we depend on NEWLIB_LIBC to build Zephyr with LORA=y. This
seems to be the only Kconfig option like that. Convert it to select
REQUIRES_FULL_LIBC instead, which will select NEWLIB_LIBC by default and
allow to use external libc as well.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
In sensors drivers, in gpio callback function :
The device structure in parameter is related to the gpio device.
Signed-off-by: laurence pasteau <laurence.pasteau@stimio.fr>
Commit id a538dcd8f8 got rid of the usage of these pointers so they are
useless now and can be removed in this drivers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert the present initialization code into initialization macros.
Since both the uart and the usart peripheral is implemented, two sets
of initialization macros are necessary.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Parsed value is expected to be in range (0, UINT32_MAX). Use strtoul
instead of strtoll, so we better match its range. In a tested
configuration this saves 380 bytes of flash with newlib and arm32
target.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This enables the ACPI_EC1 interface which is typically accessed
through ports 0x6A0 and 0x6A4 in Bios.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
For some reason, use of the DT_NUM_INST macro in this driver was not
replaced with DT_NUM_INST_STATUS_OKAY. In consequence, this driver
could not be compiled successfully. Furthermore, because this now
undefined macro had been used inside UTIL_LISTIFY, gcc was not even
able to report an error, instead the compilation just "froze".
This patch replaces UTIL_LISTIFY(DT_NUM_INST()) with more appropriate
in this context DT_INST_FOREACH_STATUS_OKAY. It also adds an apparently
missing inclusion of sys/byteorder.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
