usb: stm32: added support for USB Device mode on STM32F105xx parts
The STM32F105xx USB clock goes through a prescaler either PLL1 x2 /2 or PLL1 x2 /3, the output of this must be 48 MHz. As such, the output of PLL1 must be 48 MHz or 72 MHz. NOTE: This requires that the system is running from PLL1 (PLLCLK). Support for running from PLL2 will be implemented in the future. Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
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1 changed files with 28 additions and 1 deletions
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@ -285,7 +285,34 @@ static int usb_dc_stm32_clock_enable(void)
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LOG_ERR("Unable to set USB clock source to PLL.");
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}
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#endif /* CONFIG_CLOCK_STM32_MSI_PLL_MODE && !CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI */
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#endif /* RCC_HSI48_SUPPORT / LL_RCC_USB_CLKSOURCE_NONE */
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#elif defined(RCC_CFGR_OTGFSPRE)
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/* On STM32F105 and STM32F107 parts the USB OTGFSCLK is derived from
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* PLL1, and must result in a 48 MHz clock... the options to achieve
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* this are as below, controlled by the RCC_CFGR_OTGFSPRE bit.
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* - PLLCLK * 2 / 2 i.e: PLLCLK == 48 MHz
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* - PLLCLK * 2 / 3 i.e: PLLCLK == 72 MHz
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*
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* this requires that the system is running from PLLCLK
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*/
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if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
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switch (sys_clock_hw_cycles_per_sec()) {
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case 48000000U:
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL_DIV_2);
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break;
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case 72000000U:
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL_DIV_3);
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break;
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default:
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LOG_ERR("Unable to set USB clock source (incompatible PLLCLK rate)");
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return -EIO;
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}
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} else {
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LOG_ERR("Unable to set USB clock source (not using PLL1)");
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return -EIO;
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}
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#endif /* RCC_HSI48_SUPPORT / LL_RCC_USB_CLKSOURCE_NONE / RCC_CFGR_OTGFSPRE */
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if (clock_control_on(clk, (clock_control_subsys_t *)&pclken) != 0) {
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LOG_ERR("Unable to enable USB clock");
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