This patch adds support for Microchip's KSZ8794 DSA device, which for
switch and PHY control uses SPI communication.
This driver also provides support for handling tail tagging added and
decoded in the KSZ8794 device as well as modifying entries in the
static MAC address table.
It is also possible to use GPIO pin to reset KSZ8794 switch.
When the "reset-gpios" property is not defined, software based reset
is performed instead.
The KSZ8794 can now be used on boards which have SPI CS only available
as GPIO pin.
Signed-off-by: Stefan Bigler <stefan.bigler@securiton.ch>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch modifies Bluetooth HCI RPMsg drivers and samples to use
RPMsg Service instead of configuring OpenAMP directly in the driver
or the sample.
Co-authored-by: Piotr Szkotak <piotr.szkotak@nordicsemi.no>
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
Introduce a Kconfig variable that the SoC can set to indicate the
number of instances in Device Tree. This also fixes the accuracy of
the Elkhart Lake instance count where the code was previously assuming
up to 12 instances even though DT lists 15 nodes.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Move all PCIe-based DT nodes under a PCIe bus and take advantage of
the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Remove DW and PCA9685 PWM controller drivers as they are unmaintained
and broken.
Both drivers lack support for the pwm_get_cycles_per_sec_t API function
which was introduced in commit 56e0b53c6e
in 2016.
Fixes#18607, #18608
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Refactor slightly so we can read SFDP tables with this driver. Note
that the SFDP read command requires long frame mode transfers as data
exceeds 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
QSPI doesn't have a different length expectation than normal SPI, so
introducing a new name for an existing name is unnecessary. Also
replace the constant with the actual buffer size where appropriate, in
somebody changes the the buffer definition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The interface used to send commands supports only a command followed
by 8 bytes of data transfer. Reject attempts to do more, as the
result will be a successful transfer of only the first 8 bytes.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Not all special commands require that a write-enable be issued first.
Allow the caller to decide.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW16 provides information on mechanisms to enter and exit 4-Byte
address modes, returning the device to reset state, and how to
manipulate the values in the first status register.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Instead of having a hard-coded maximum instance count, introduce a
Kconfig variable for it. The inclusion of the per-instance header
files is solved by having them chain-include each other with a
pre-processor condition that checks if the current header file is the
last one or not.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The reg-shift support was quite broken in that the code only looked
for this property on instance 0. Now we support the property on any
node which might declare it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Take advantage of DT_INST_FOREACH_STATUS_OKAY() to look for DLF and
PCP properties on any matching nodes with "okay" status.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use a dependency block instead of specifying a UART_NS16550 dependency
for each individual opton. This doesn't save many lines right now, but
may do so once more options are added.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add initial implementation of the uart async api
for stm32 mcus. This uses the dma controller
in normal mode for reception. In addition, to detect
reception of bytes we enable the idle line detection
interrupt.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Signed-off-by: Jun Li <jun.r.li@intel.com>
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move iis2dlpc trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Simplify the switch case on trigger types (SENSOR_TRIG_DRDY and
SENSOR_TRIG_TAP) inside iis2dlpc_enable_int().
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This patch replace CONFIG_GPIO_SIFIVE_N_PRIORITY into interrupt-cell
of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch replace CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY into
interrupt-cell of device-tree to set IRQ priority.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
In #31192 stm32 uart driver uart_irq_rx/tx_ready functions were
modified to take into account status of irq.
While it seems wlecome for TX (based on uart client's implementation),
this is not correct for RX.
Revert change in uart_stm32_irq_rx_ready function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace marco function, defined(), with IS_ENABLED() in host sub-devices
driver implementation. In this PR, we won't replace the macros which
cause -Wimplicit-function-declaration warning if related configuration
is not enabled or its type is not boolean..
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for DMA based STM32 QSPI NOR flash controller.
Driver configures both NOR flash and also QSPI hardware block.
Reuses existing jesd216 library.
QSPI hardware block handling is done through the use of Cube HAL API.
This requires the use of HAL interface also for DMA besides zephyr
DMA driver.
Zephyr DMA driver is used only for IRQ routing while HAL driver
handles the IP block. To achieve this it is required to:
-Configure both Cube and Zephyr drivers at init.
-Inform Zephyr driver that current channel handling will be done
by another instance and only a limited configuration should be done.
For this last part, a unused parameter is overridden in order to
transmit the information.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
AHB3 bus support is added for compatible series.
Additionaly, fix condition for AHB2 support and fix
formatting
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
According to AT commands manual, no wait after prompt '@'
is required if using AT+USOST commmand (aka. sendto,
only used with UDP).
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
core-macros.h includes other files not part of the xtensa HAL, make this
esp32 specific
Fixes#31301
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
