Use mm_reg_t for DesignWare I2C MMIO register addresses to avoid
truncating addresses above 4 GiB on 64-bit systems.
Keep register values as uint32_t since the controller still uses
32-bit register accesses.
Signed-off-by: Liwen Wu <liwen.wu@spacemit.com>
- handled return value of target callbacks.
- Rename tgt_rx_data to tgt_xfer_data for clarity.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
The systimer is a free-running counter plus a one-shot alarm, so a
COMPARE_ORDERED backend. The driver keeps the counter read and the alarm
write, now timer_driver_cycle_get() and timer_driver_set_compare(), and
the core takes over the tick accounting: last_count, the elapsed-ticks
helper, the tick-aligned deadline computation with its round-up and the
range clamp all go.
The unit counter is 52 bits wide, so the driver states that width and the
core masks its deltas at the counter's true wrap.
The driver's own cycle getters go. Both were guarded against a read after
sys_clock_disable() deinitialized the HAL; that guard now lives in
timer_driver_cycle_get(), which the core's getters go through, and the
arming primitive carries it too. It reports the counter value sampled at
disable rather than zero, so a read landing after it holds the elapsed
span instead of stepping the counter backwards.
MIN_DELAY goes. Every SoC this driver builds for defines
SYSTIMER_LL_ALARM_MISS_COMPENSATE, which is the peripheral raising an
alarm armed at or behind the counter rather than losing it, so a target
that is close or already passed needs no push forward. Espressif's own
systimer_hal_set_alarm_target() writes the target bare on those parts and
keeps a write-and-recheck loop only for the ones without the bit, none of
which this driver covers. Dropping the floor also takes a counter read
off every arm, which on this HAL is a snapshot request, a spin on the
valid bit and a triple read.
The low-power handoff moves from the idle argument of
sys_clock_set_timeout() to sys_clock_idle_enter(), which arms the wakeup
through the core and then hands over to the LPM hook.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The help text of VIDEO_BUFFER_POOL_ZEPHYR_REGION points the reader at
CONFIG_VIDEO_BUFFER_ZEPHYR_REGION_NAME, which does not exist. The option
is declared two lines below as VIDEO_BUFFER_POOL_ZEPHYR_REGION_NAME and
is the name used everywhere else: subsys/video/buffer.c and the board
defconfigs for stm32h7s78_dk and stm32n6570_dk.
Fix the name in the help text so it matches the declared option.
Signed-off-by: Daniel M'BOUYOU <danielmbouyou@gmail.com>
cf1133_init() registers the GPIO callback and configures the interrupt,
or starts the polling timer, before calling cf1133_ts_init(), which is
the only assigner of data->pixel_length. When it fails, init returns with
the callback still registered and the timer still running.
cf1133_process() sizes its read as 1 + SUPPORTED_POINT * pixel_length,
one byte when pixel_length is 0, then unconditionally dereferences
buffer[1..3] for the valid bit and both coordinates. A transient NAK at
boot therefore leaves every subsequent interrupt edge, or every 10 ms
timer tick, decoding uninitialized stack: whenever bit 7 of the garbage
is set the driver emits BTN_TOUCH=1 with a random coordinate for the life
of the system. The same window exists at startup before ts_init() runs.
Probe the controller first, right after k_work_init(); it only needs the
I2C bus, which is already validated. Nothing that can fail then follows
the arming step.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Check embedded memory in peci_msg before using it to avoid
a user thread to read and write arbitrary kernel memory through
the syscall.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Set the NWP power profile at boot, rather than postponing it until
Bluetooth is enabled. The workaround to postpone it is no longer
needed, as recent NWP firmware versions support setting power
profile prior to configuring Bluetooth TX power.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DMADRV HAL is deprecated, switch to DMA manager HAL for
channel allocation bookkeeping.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Adapt Series 2 HCI driver to changes in SiSDK v2026.6.0. The
functions to send and receive events have been renamed, and
the buffer memory is configured in a different way.
The radio also requires PHY configuration files to be separately
compiled, they are no longer built in to the library.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Fix "warning: suggest parentheses around comparison in operand
of '&' [-Wparentheses]" by adding the parentheses.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add driver for PIT (Periodic Interval Timer), only supports tickful
kernel mode (CONFIG_TICKLESS_KERNEL=n).
Signed-off-by: Tony Han <tony.han@microchip.com>
Implement SENSOR_ASYNC_API for the MS5637 driver using RTIO
submission chains for non-blocking pressure/temperature reads.
- Add RTIO SQE chain helper (ms5637_prep_conv_chain) to
reduce duplication between pressure and temperature paths
- Add sensor data decoder with q31 output format
- Refactor ms5637_compensate to accept calibration struct
and output reading pointer, eliminating dependency on the
full ms5637_data struct for use in decoder context
- Add Kconfig selections for I2C_RTIO and RTIO_OP_DELAY
when SENSOR_ASYNC_API is enabled
- Fix CMakeLists.txt to use CONFIG_SENSOR_ASYNC_API
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Assisted-by: Claude:claude-opus-4.7
Allow the Raspberry Pi BCM2711 framebuffer driver to configure the
initial pixel format through devicetree. Add support for ARGB8888
and ABGR8888 formats.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Perform the required cache maintenance before and after ADMA
transfers when the data cache is enabled.
Direct DMA read buffers must be aligned to the data cache line size because
invalidating a partial cache line may discard unrelated dirty data.
Use a cache-line-aligned bounce buffer for small reads whose transfer
size is not a multiple of the cache line size. This allows commands
such as the 4-byte MMC SEND_WRITE_PROT command to use ADMA safely.
Set the SDHC buffer alignment to the greater of the configured
data cache line size and the controller's minimum 32-byte
alignment requirement.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
dwc2_core_init_host_gusbcfg() reads GUSBCFG register value, modifies the
register to force host mode but does not read the actual register value
back. Using an outdated value later the dwc2_core_init_host_gusbcfg()
reverts to device mode. The bug is only observable on boards with
ID-pin not grounded.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add initial support for the NeoChrom GPU2D hardware accelerator.
This driver provides basic initialization and configuration of
the GPU2D engine.
Enables hardware-accelerated 2D rendering support for use with higher-level
graphics subsystems such as LVGL.
Signed-off-by: Radhika Changela <radhika.changela@siliconsignals.io>
gpio drivers need to have struct gpio_driver_config and
struct gpio_driver_data at the first position of the data
and config struct.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Enabling proper zoom/scaling for windowed resolutions;
e.g. smaller than uxga
That makes camera's ISP to downscale frame to a desired resolution
Signed-off-by: Roman Pustobaiev <romanpustobayev@gmail.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
There is no standard way to launch a secondary CPU out of its quiescent
state. While ARM Cortex-A cores use standardized secondary cpu launch
methods like PSCI or spin-tables, other multi-core SoC's (eg.
raspberrypi rp2350, nxp lpc55s69, etc) enable-methods are entirely
vendor-specific.
The devicetree specification section 3.8.1 describes the enable-method
property of a cpus/cpu* node. It may have the value "[vendor],[method]"
which describes the vendors-specific method by which a CPU is released
from a disabled state.
Remove enum from enable-method binding and update DT macros that relied
on enable-method being an enum type property.
Document the [vendor],[method] value in the enable-method property of
cpu.yaml.
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
CONFIG_I2C_RTIO=y enables CONFIG_I2C_STM32_INTERRUPT since STM32 I2C RTIO
drivers are only supported with interrupts enabled.
Remove the sentence in I2C_STM32_V2 config symbol description about
I2C_STM32_INTERRUPT selection since it is already explicitly stated by
the 'select' command and makes I2C_STM32_V2 description more consistent
regarding I2C_STM32_V1 description.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add the HCI driver that carries Bluetooth traffic over the
esp-hosted-mcu transport core, so Wi-Fi and Bluetooth share the
single link to the coprocessor. The driver asks the coprocessor
to initialise and enable its controller, then acts as a raw H4
bridge.
Received frames are copied into a slab slot on the shared receive
thread and rebuilt on a dedicated delivery thread, so waiting on
a host buffer pool cannot stall the Wi-Fi path. The framed
transport adds call depth on the tx processor thread, which runs
the driver send path, so its stack default is raised.
The coprocessor firmware advertises the controller to host flow
control commands but rejects them, so the binding sets the
no-flow-control quirk by default.
Extended advertising is left to the application. The coprocessor
is a separate part whose Bluetooth generation is not known when
the host is built: an esp32 provides Bluetooth 4.2 and has none,
while the riscv parts provide 5.0. Keep the legacy advertising
commands available so either generation works.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the Wi-Fi driver for an Espressif coprocessor running
esp-hosted-mcu firmware. The driver registers station and access point
interfaces with the network stack and carries their frames over the
esp-hosted-mcu transport core.
Management operations are driven over RPC against the coprocessor
esp_wifi API: scan, connect and disconnect, access point enable and
disable, mode and channel, power save, connected access point details
and station deauthentication. Connection results and station events
are reported asynchronously from the coprocessor event stream.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the transport core shared by the esp-hosted-mcu Wi-Fi and
Bluetooth drivers. The core owns the framing, the checksum, the
sequence counter and the RPC request and response matching, and it
demuxes received frames to the registered interface consumers.
Transports are pure byte movers behind a four function vtable, so the
protocol handling stays in one place. Both an sdio backend, driving
the coprocessor SLC register window, and a full duplex spi backend
with reset, handshake and data-ready lines are provided; the transport
is selected at build time from devicetree.
At init the core asks the coprocessor for its firmware version and
logs it, falling back to the version carried in the boot event when
the firmware is too old to answer. The expected version is only a
Kconfig declaration: the firmware is flashed to a separate chip, so
a mismatch is warned about and never fails init.
The boot event also carries the SDIO datapath mode. When the
coprocessor aggregates frames it pads each one to a four-byte
boundary, so the receive walk reads the advertised mode and steps by
the aligned stride; a byte-tight coprocessor is unaffected.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
A UART that woke the SoC keeps PM_STATE_SUSPEND_TO_IDLE locked forever
once the hardware receiver timeout is in use.
The WKUP interrupt takes the lock and sets rx_woken. The IDLE arm of
uart_stm32_isr() would release it, but set_timeout_itr() disables the
IDLE interrupt when it programs RTOR, so the RTO arm reports the end of
reception instead and only clears the flag and flushes. The lock is never
released, so the system never enters a Stop state again.
Move acquire and release into helpers and call them from both paths, so
the behaviour at the end of reception is consistent.
Also move enable_wakeup_line out of the block with the PM policy helpers.
Tested on a nucleo_l476rg, cyclic asynchronous reception with PM enabled.
Fixes: #116273
Signed-off-by: Eden Frosst <eden.frosst@rbr-global.com>
Add a driver for the Aesc Silicon SPI XIP controller, exposing the
execute-in-place mapped SPI NOR flash as a Zephyr flash device. The
flash region is a soc-nv-flash child of the "aesc,spi-flash-controller"
node.
Reads are served from the memory-mapped XIP window. Programming is not
supported yet, so write() and erase() return -ENOSYS.
When the "aesc,quad-mode" property is set, the driver switches the
controller and flash to quad read mode at init, skipping the
reconfigure when a bootloader already enabled it.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Convert the Xtensa CCOUNT/CCOMPARE timer to system_timer_generic.h.
CCOMPARE fires only on CCOUNT == CCOMPARE, so an already-past target is
missed until CCOUNT wraps: that is the COMPARE_EXACT backend, whose
verify loop replaces the minimum-delay bump the driver applied by hand.
The driver keeps timer_driver_cycle_get() (CCOUNT) and
timer_driver_set_compare() (CCOMPARE), and the core takes over the tick
accounting: the last_count baseline, the tickful re-arm and the
sys_clock_elapsed()/set_timeout() tick math all go. smp_timer_init()
primes the per-CPU timer through timer_core_smp_prime().
ccount() still adds the low-power compensation offset, so the cycle count
and every announced delta pick it up. The Espressif LPM hook
(CONFIG_XTENSA_TIMER_LPM_TIMER_HOOK) moves to sys_clock_idle_enter() and
folds the missed cycles into that offset; the non-low-power idle path
drops to the weak sys_clock_idle_enter() default, which arms through
sys_clock_set_timeout().
The low-power exit hands its recovered span to the core directly rather
than folding it into the counter for the announce to find. CCOUNT is 32
bits, so a sleep can outrun what the masked delta resolves, which at
240 MHz is under nine seconds. The compensation still takes the same
span, so the counter stays in step and what CCOUNT did see is left for
the next announce.
kernel.timer.sloppy_idle gains qemu_xtensa/dc233c: with nothing pending
the core arms the longest interval it allows, so the time base keeps
running.
timer_api, context, sleep and tickless pass on qemu_xtensa/dc233c.
Build-verified on esp32 with the LPM hook (CONFIG_PM=y) and with SMP.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Writing CCOMPARE is what clears the pending timer interrupt. The ISR
never wrote it in tickless mode, relying on sys_clock_set_timeout()
being reached after the announce to do so.
That holds only as long as something does call it. On SMP each CPU has
its own CCOMPARE, but sys_clock_announce_locked() returns early on all
but the announcing one, so the rest return from the ISR with the
interrupt still pending and take it again immediately. Nothing
guarantees a new deadline is armed on UP either: with no timeout pending
the kernel may legitimately choose not to.
Write a compare one behind the current count on entry. That clears the
interrupt, and since the match is on equality it also puts the next one a
whole counter period away, which is as far as a 32-bit comparator
reaches. The arming path overwrites it in the normal case.
Split the raw CCOUNT read out of ccount() so the ISR can form that value
without the low-power compensation the cycle domain carries.
Fixes: #115442
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The implementation of EM4 wakeup pin support assumed all ports
have at least one EM4WU capable pin. Support the case where
EM4WU pins may not be available on every port.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
