This commit replaces driver hard coded clk bus and enr definitions with
definitions from device tree.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit fixes missing pclken member if used for h7 series.
Additionally to the check if instance 0 of compatible
st_stm32_flash_controller has defined a clock,
this needs to be checked for compatible st_stm32h7_flash_controller.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
It was found that npcx7 series' GPIOs which support low-voltage power
supply, there is an excessive power consumption if they are selected to
low-voltage mode and their input voltage is 1.8V.
To avoid this excessive power consumption, this CL suspends the
connection between IO pads and hardware instances before ec enters deep
sleep mode. Then restore them after waking up.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Change to use macro DT_FOREACH_CHILD_STATUS_OKAY to avoid routing the
interrupts to the disabled cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Current Cypress PSoC-6 serial driver only works using polling mode.
Add serial driver interrupt routines to allow use of interrupts.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Support both 24-bit and 32-bit address values when constructing the
device command. Note that some commands require 24-bit address
regardless of mode, and some require 32-bit addresses regardless of
mode, so provide command-specific overrides of a generic (but not yet
configurable) default address size.
With this we no longer need a special interface for READ_SFDP which
uses a 24-bit address but with a wait state introduced by clocking out
a fifth command byte.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This driver abstracts most access through a generic function that
supports both read and write with and without address components in
the command. Rework this so that instead of distinct arguments
specifying the combination of features there's a flag set that will
allow more combinations to be specified.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Fixes#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
Kconfig symbol is used in hal_stm32 module to define Cube HAL
symbol HSE_VALUE (cf hal_stm32/stm32cube/CMakeLists.txt).
Due to this specific usage, this symbol should be kept. As a
consequence it could not be replaced by dts equivalent but we can
use dts to configure it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
For testing purposes, add simulated PTP clock device to e1000
Ethernet driver that is used in qemu_x86 board. The PTP clock
does nothing useful as there is no real hw behind this device.
We just emulate the clock in order to do some SO_TXTIME testing.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
It is possible that user wants to access PTP clock but does
not need gPTP support. The networking txtime sample does exactly
this.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If there is a UARTE receive error (e.g. framing or break), the RXTO
event may never come. Check error event too, to avoid an infinite loop.
Signed-off-by: Jim Paris <jim@jim.sh>
Replace all existing deprecated API with the recommended alternative.
Fixes#34102
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Fix stm32_dma_is_irq_active not checking the IRQ status(IsEnabled) for
active interrupts.
While the transfer-complete, half-transfer comp. and transfer-error
is_XX_irq_active() functions check for IRQ status (IsEnabled),
ORing the result with dma_stm32_is_gi_active() overrides the
status check as gi is always 1 in case any of these flags is active.
Related to commit 96c92ed93f.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Use LL_DMAMUX_CHANNEL_x defines instead of DMAMUX_CSR_SOF7x to check
if corresponding LL_DMAMUX_IsActiveFlag_SOx and LL_DMAMUX_ClearFlag_SOx
inline functions exist and should be added to func_ll_is_active_so[]
and func_ll_clear_so[].
The HAL of some socs uses the same flag to decide which registers exist
on a specific soc. And the same defines are used for table_ll_channel[]
initializations.
This is necessary because DMAMUX_CSR_SOF5 and DMAMUX_CSR_SOF6 were
wrongly added in the HALs soc header file for some stm32g0 socs,
therefore without this change some stm32g0 socs couldn't compile.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the existing driver to support STM32G0 series.
It enables the DMA_STM32_SHARED_IRQS flag for g0 series, such that
all interrupts are handled in a shared isr to avoid irq conflicts.
The shared isr is extended to be able to handle irqs from more than one
dma instance.
Furthermore the config_irq function of instance 1, which connects to the
irqs, was reworked to avoid irq conflicts when 2 dma instances on
stm32f0, or stm32g0 are enabled:
While dma1 has one exclusive irq for channel 1, and one irq for dma1
channels 2 and 3, all other channels share the same irq.
Therefore it is currently not possible to enable dma2 without enabling
dma1 at the same time, without getting an build errror due to an irq
conflict.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Not all STM32 Series can enable a dedicated clock for dmamux.
In stm32g0 series for example the clock is enabled automatically
as long as either DMA1 or DMA2 is enabled.
This commit changes dmamux driver to cope with socs that don't have
defined a clocks property. Therefore it moves the config(and data)
struct into the c file to be able to use DT_INST_NODE_HAS_PROP macro.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In SMP, MPID is mybe not equal to cpu logic ID, so can't
use MPID to get rdist base address from gic_rdists[], this
patch get logic ID from arch_curr_cpu()->id, and
find current CPU's rdist base address from:
gic_rdists[cpu_logic_id]
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
For a zero-length transfer, the STOP task is not triggered
automatically by the shortcut with the event that signals
the transfer end because such event is not generated.
Trigger this task "manually" to prevent the driver getting
stuck after the address byte is acknowledged.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for delayed transmission of frames for the CSL
Transmitter OpenThread function.
Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
When BT and WiFi coexists, IRAM usage increases a lot.
Add configuration that allow wifi symbols
to be placed in flash, freeing space in IRAM.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
TWDT0 is loaded with a new value and the counter restarts counting with
it by written RST bit in Timer Control register (T0CSR) to 1. Then, the
RST bit in T0CSR register is cleared automatically on the 2nd rising
edge of T0IN clock. Since TWCP is set to 1:32, the maximum time that RST
bit is unset is 32 * (1 / 32768) ~= 980us.
Polling this bit within a critical section in current npcx watchdog
driver isn't a good approach since it might block the other interrupts
need to service them in time. This CL introduces a timeout mechanism and
removes the critical section to improve this disadvantage. Consider the
clock tolerance, 2 ms is a suitable timeout value for RST bit. We also
remove polling for WD_RUN bit in T0CSR. Npcx watchdog needs serval LFCLK
(32k Hz) clocks to stop watchdog. 1 ms is long enough for the timeout
mechanism.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
NPCX PWM supports output buffet select to push-pull or open-drain. Add
output buffer select option 'drive-open-drain' in devicetree for NPCX
PWM. If set, the PWM output will be configured as open-drain. If not
set, defaults to push-pull.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)
In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX host access IRQ enables before entering deep sleep. The pending
bit lets chip wake up from sleep immediately. Clear host access IRQ
pending bit before enabling.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There are no boards that need hard-coded interrupts so just remove this
build-time conditional branch. The way going forward is that all PCIe
devices should always use PCIE_IRQ_DETECT.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Move emul.h out of the top level include/ dir into
include/drivers/emul.h and deprecated the old location.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.
Controller can handle up to 32 GPIOs per banks.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Move ctx structure from struct data to struct config, so that
it can be filled at compile time and we could get rid of the bus
init routines.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
