In the current USB device support, the sizes of bulk endpoint
are mostly configure through Kconfig and do not care if a device
is high-speed capable. The information if a USB device controller
supports high-speed comes from devicetree. Add a Kconfig option to
map this information and configure bulk endpoint sizes
accordingly.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Define a custom IEEE802154 based L2. The user can then use those symbols
to implement their own 802.15.4 based L2, based on those symbols, w/o a
need to modify the Zephyr tree.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Some 802.15.4 L2 implementations expect that FCS length is included in
the overall packet length while others not. Allow to configure this
behavior, based on the selected upper layer.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Introduce a common config for all 802.15.4 based L2 implementations.
This way, any custom 15.4 L2 implementation will be able to
automatically enable use 15.4 driver, w/o a need to modify the actual
Kconfig.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The CAVS_IDC_IPM driver happens to be used only on non-2.5 hardware,
but it's best to be clear in the conditional compilation when we're
talking about hardware-dependencies and when we mean software
configuration. This was mixed up in a few spots.
Also fix a warning that creeps in on non-default drivers choices about
an undeclared ipm function.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
All the in-use contents of these files have now been moved to the
intel_adsp core, and they are configured via devicetree and kconfig.
Remove the legacy headers.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is dead code. It's based on the cAVS "IPC" mechanism to allow
communication to and from the host CPU. But there is no test rig in
the Zephyr tree for the protocol defined. And in fact the only
Zephyr-based user of the IPC mechanism (Sound Open Firmware) has its
own IPC driver and speaks its own protocol with the host kernel. That
driver needs to migrate into Zephyr soon and this legacy bit is just
confusing.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Recent work to this platform added a new, cleaner low level API to the
interrupt controller. Replace the hand-cooked register access with
that. This is still not as good as having proper multicore support in
the intc_cavs driver, but it's at least better.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Device data is cleared on deinitialization. This operation removes
some important information. Let's restore the defaults each time
the device is initialized.
Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
fix uart_sam0_irq_update to only clear the RXS bit by writing only the
RXS bitflag to the INTFLAG register. Performing an |= opperation
with the bitflag for RXS incorrectly clears all pending interrupts set
since writing 1 to a INTFLAG clears that bit field. This causes a race
condition on when TXC will be cleared before all bytes have finished
being clocked out on tx and TXC being set 1 again. If tx finishes first,
any driver using uart_irq_tx_complete will deadlock the system.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
sam0 does not currently have a uart_irq_tx_complete method for interrupt
driven mode.
This is especially important since the sam0 platform has seperate
interrupt signals for TX data register empty and TX complete therefore
the TX register being empty does not nessisarily mean the data has been
shifted out.
Drivers should check uart_irq_tx_complete if it needs to guarantee
that the data has been fully transmitted in a hardware agnostic way.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
Aim of this change is to remove the need for the pinmux driver
on stm32f1 series to access the base address of the pinmux owner
device.
This is achieved by a modification in the device tree pin definition.
Instead of providing a generic information on type of the remap
(such as NO_REMAP, PARTIAL_REMAP, FULL_REMAP), the remap field
encodes all the information required to perform the remap register
configuration:
-Address of the targeted remap register in AFIO peripheral
-Position of the remap configuration in the remap register
-Mask used for the remap configuration encoding
-Value of the expected remap configuration.
All the possible remap configurations are encoded and predefined
in a new stm32f1-afio.h dt-bindings include.
To match this new configuration, all stm32f1 -pinctrl.dtsi should
be regenerated to use these new remap definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review pinmux macro definition to a more portable format,
in preparation for new remap information encoding on stm32f1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
A lock was added to manage situation where the API poll_out and irq API
are used in same time.
Signed-off-by: Julien D'ascenzio <julien.dascenzio@paratronic.fr>
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.
Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.
Fixes#40133
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extends STM32 PWM driver to support capturing pulse width, period,
or both.
The approach used is based on the PWM Input sections in reference
manual RM0351 by ST in the chapters on timers.
The LL library by ST is used for all extensions to the driver.
Only the disco_l475_iot1 board was available for testing on hardware,
using tests/drivers/pwm/pwm_loopback.
Since timers are a generic component, it is assumed that other STM32
boards will behave the same
Fixes#39394
Signed-off-by: Tilmann Unte <unte@es-augsburg.de>
Current driver set a fixed prescaler value for the lpuart
that caused certain baudrate configurations to fail due to
LPUARTDIV overflow the LPUART_BRR register.
This PR attempt to calculate a suitable PRESCALER for the
selected baudrate, throws error and return if it couldn't get
an optimal one.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Clock ISR was running 2x the frequency.
Also fixes clock_get_cycle which was returning
wrong values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Check return value from recv() passed by usbip_recv().
Fixes: #39849Fixes: #39869
Coverity-CID: 240221
Coverity-CID: 240244
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
It does not make sense to use branch coverage with macro LOG_ERR().
It is still covered with line coverage.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
HTS221 is a humidity and temperature sensor (thus HTS) that can be wired
on i2c or SPI bus. On SPI bus however, it uses the 3-wire mode, aka:
half-duplex.
Now that SPI API exposes half duplex operation, let's enable the SPI bus
on that sensor.
Let's move to a better DTS integrated driver as well, and also use
stmemsc interface.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is meant to expose half/full duplex configuration option on regular
configuration. So far, dual/quad/octal are not exactly supported, as it
would require extensions to the SPI buffer for a full support.
So moving these modes to an extended operation attribute
(32 vs 16 bits), disabled by default.
And exposing half/full duplex configuration bit. Full duplex being the
default option.
Fixes#19134
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Port some drivers to the recently introduced macros to showcase its
usage and be able to do some initial testing (nRF52840).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The macro already mentions in the docstrings that PM is not supported:
"Invokes DEVICE_DEFINE() with no power management support".
This patch removed the PM entry from the macro and ajusts its uses.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Define the device using DEVICE_DEFINE macro, so that a single option can
be used regardless of PM being enabled or not.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since there are no more users and dependencies of
Kconfig option USB_UART_CONSOLE in the tree,
remove the remains and the option USB_UART_CONSOLE.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Do not change init level and priority of console driver
if Kconfig option CONFIG_USB_UART_CONSOLE is enabled because
commit 37f4d9ba63
("usb: cdc_acm: rework cdc_acm_poll_out to non-blocking")
changed CDC ACM UART driver so that it more closely mimics
the real controller and CDC ACM UART driver now uses the same
init level and priority as regular serial driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit fixes dual bank flash handling on stm32g0 targets.
In contrast to other Series (G4, L5) the flash page size does not change
in single bank configuration (2KiB in both configurations).
nSWAP_BANK:
While the reference manual(RM) only documents:
"This bit selects the bank that is the subject of empty check upon boot"
as expected, this behaves similar to BFB2 on G4 and SWAP_BANK on L5.
It has been observed that this bit swaps the address mapping of bank1
and bank2, regardless of DUAL_BANK bit being set or not.
As documented in the RM the nSWAP_BANK bit is ignored when the BOOT_LOOK
bit is set. This applies to the empty check as well as the address
mapping.
On this Series FLASH_CR_BKER must be set in single-bank as well as
dual-bank configuration for erase operations on bank2 regardless of
the swap status.
On a G0B1RE (dev-id: 0x467) I could not observe a difference between
DUAL_BANK flash option bit set and not.
It this may be different on 256KiB Flash targets.
The HAL indicates that "FLASH_SALES_TYPE_0" only uses a single bank if
OB_DUAL_BANK_VALUE is not set, but as I don't know which SoC this is
and I can't test the behaviour and the driver does not take this into
account.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit makes no functional changes, it only refactors the
driver such that dual bank flash handling can be easily added.
Instead of using HAL macros directly in the code, new macros
with STM32G0 prefix are defined.
The erase_page function gets passed the offset instead of the page,
and the FLASH CR reg is written once with all erase parameters.
flash_stm32_wait_flash_idle is already called before each
write to CR, consequently it is also made sure CFGBSY flag
is not set.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
