The initialization code was updating the freq field in the const
declared config block at runtime because the frequency is not
known at compile time. Add a get_freq() api call to handle any
runtime requests for frequency.
fixes#41953
Signed-off-by: David Leach <david.leach@nxp.com>
Device 'data' variable name was incorrect due to recent treewide naming
cleanups. Fix variable name to fix build error.
Fixes#42118
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Let's have dev_data for dev->data so it will not conflict with struct
call_back data variable.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Coverity identified valid error where the routine does a NULL
check for two different pointers after they have been dereferenced.
fixes#39868fixes#39874
Signed-off-by: David Leach <david.leach@nxp.com>
Current version of STM32 PTP clock reads current PTP time by querying
second and nanosecond registers sequentially. It is possible for second
to roll over between reading second and nanosecond registers, causing
returned time to be off by a second. This bugfix resolves that issue.
Signed-off-by: Alex Sergeev <asergeev@carbonrobotics.com>
Exposes the RC register so that the initial value can be set in
the device tree. This is useful in the case where the timer
generates an event but an interrupt is not required.
e.g generate event to sample adc on RC register match.
Tested on Atmel SMART SAM E70 Xplained Ultra board
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
Current gpio and uart initialization level is set to
PRE_KERNEL_2, which won't let uart_console subsystem
to init its hook properly as it has same level.
Prioritize uart and gpio so that the console hooks
are properly initialized.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Current uart driver implementation is incompleted regarding the
usage of DT_INST_FOREACH_STATUS_OKAY. If uart0 and uart2 are selected,
build breaks due to peripheral number ordering, which would be
0 and 1 in this case. This fix PR fix this by re-working the macros
and setting proper uart peripheral instances in DTSI, required for signal
routing configuration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update the Kconfig configuration items used to determine if the current
target is based on the Zynq-7000 SoC family as part of the re-organi-
zation of the Zynq-7000 SoC configuration data.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Update the Kconfig configuration items used to determine if the current
target is based on the Zynq-7000 SoC family as part of the re-organi-
zation of the Zynq-7000 SoC configuration data.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
PR #41918 introduced a few warnings and build failure due to
missing data cofniguration and DEV_CFG() removal.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
After #41918, DEV_CFG removal triggered discard qualifer warning
during build. As uart_hal functions don't required const qualifier
and uart_context_hal_t has modified data, this PR moves hal instace
to data struct instead of config struct.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
After #41918, build started to warn discard qualifer
in config struct. This adds const into those structs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated H4 driver to initialize setup function. Finally bt_h4_vnd_setup
function must be implemented in vendor-specific HCI extension module if
CONFIG_BT_HCI_SETUP is enabled.
BT_HCI_SETUP feature is useful when the BT Controller requires execution
of the vendor-specific commands sequence to initialize the BT Controller
before the BT Host executes a Reset sequence.
To enable this feature the CONFIG_BT_HCI_SETUP should be enable.
Fixes#41140
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
- Added config BT_HCI_SETUP to enable HCI vendor-specific Setup feature,
- Added pointer to 'setup' function in bt_hci_driver structure.
BT_HCI_SETUP feature is useful when the BT Controller requires execution
of the vendor-specific commands sequence to initialize the BT Controller
before the BT Host executes a Reset sequence. To enable this feature the
CONFIG_BT_HCI_SETUP should be enable.
Fixes#41140
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Address the issue mentioned in zephyrproject-rtos#7412
Using printf() with "%x" to print an off_t value produces the
following warning:
format '%x' expects 'unsigned int', argument has type 'long int'
228 | LOG_DBG("Erasing sector at 0x%08x", offset);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~
| |
| off_t {aka long int}
In newlib off_t is long. Even though both int and long are 4 bytes wide
in the architecture in use, GCC wants to see "%lx" to printf() a long.
Using "%"PRIx32 still produces the same warning because PRIx32
(from inttypes.h) still expands to simply an "x" and not "lx".
PR zephyrproject-rtos#40004 has solved this by casting offset to
ssize_t. The same solution is emulated here.
Signed-off-by: Milind Paranjpe <milind@whisper.ai>
Fixed#41945
NO_PINT_INT can have the same value as a specific pin.
E.G. For 1 byte pint_pin_int_t it equaled interrupt1.
Now is instead always 1 higher than the highest pin.
Expects fsl to keep setting values from 0 to
(number of connected outputs - 1)
Signed-off-by: Martin Koehler <koehler@metratec.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
* New m_can driver variant for STM32H7, as it uses the complete m_can
register set.
* Fix definitions for CAN_MCAN_RXF0S_F0FL, CAN_MCAN_TXEFC_EFSA_POS.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
1. Update to add support for Flexcomm8-13.
2. Fix the clock control driver, the enclosing #define
was incorrect.
3. Identify HS_SPI port using the appropriate Register
define
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
For multicore devices like nRF53, shim layer part of setting mac keys
and frame counters is called on application core where
CONFIG_NRF_802154_ENCRYPTION is disabled (the define concerns radio
driver for net core). This commit replaces
CONFIG_NRF_802154_ENCRYPTION with CONFIG_IEEE802154_2015.
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
This commit adds support for tickless operation on the MIPS CP0 timer.
The code closely follows the Xtensa and RISCV timer drivers.
All tests pass.
Signed-off-by: Remy Luisant <remy@luisant.ca>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
In order to preserve stack, this replaces the single-bus enumeration
loop by a stack based non-recursive pcie hierarchy iteration.
Each stack entry contains a bridge bus enumeration state.
When a bridge endpoint is detected on the current bus, it is
configured and this new bus is pushed on top of the stack in
order to be enumerated at next loop.
When enumeration ends on the bus, the current bus state is
removed from the stack to continue enumeration on the previous
bus.
This enumeration affects a sequential bus number to each new
bus detected in the same order as Linux & U-Boot does.
In this hierarchy:
[0 1 2 ... 31]
| | |
EP | |
| |
[0 1 ... 31] [0 ... 31]
| | |
| EP |
| [0 ... 31]
[0 ... 31] |
| EP
EP
We will get the following BDFs enumeration order:
00:00.0 Endpoint
00:01.0 Bridge => Bus primary 0 secondary 1
01:00.0 Bridge => Bus primary 1 secondary 2
02:00.0 Endpoint
... Bus secondary 2 => subordinate 2
01:01.0 Endpoint
... Bus secondary 1 => subordinate 2
00:02.0 Bridge => Bus primary 0 secondary 3
03:00.0 Bridge => Bus primary 3 secondary 4
04:00.0 Endpoint
... Bus secondary 4 => subordinate 4
... Bus secondary 3 => subordinate 4
The gives the following primary/secondary/subordinate map:
Bus 0 [0 1 2 ... 31]
| | |
| [0:1->2] [0:3->4]
EP 00:00.0 | |
| |
Bus 1 [0 1 ... 31] Bus 3 [0 ... 31]
| | |
| EP 01:01.0 |
[1:2->2] [3:4->4]
| |
| Bus 4 [0 ... 31]
Bus 2 [0 ... 31] |
| EP 04:00.0
EP 02:00.0
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds setup of Type 1 bridge endpoints in two steps, first when
endpoint is detected and secondly when enumerating the next endpoint.
First, the code configures the bus primary & secondary number and 0xff
as subordinate to redirect all PCIe messages to this bus.
Then memory & I/O base are programmed by getting the current allocation
bases.
Finally, now right away, we program the subordinate to the max bus
number under the bridge, here the same, and the memory & I/O limit,
here lower than the base.
This doesn't make the bridge totally usable, enumeration would work
bus not for nested bridges and BARs wouldn't be accessible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to prepare support for bridges enumeration, split out the
actual endpoint enumeration code out of the enumeration loop.
Pass a skip_next_func boolean to indicate if the current endpoint
is multifunction of not, to continue to next dev or next function.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Type 1 endpoints has 2 BARs are the same position as the Type 0
BARS 0 & 1, so reuse the generic_pcie_ctrl_type0_enumerate_bars()
for both types by passing the number of possible BARs on the endpoint.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Some drivers explicitely casted data/config from void * to the
corresponding type. However, this is unnecessary and, in many drivers it
has been misused to drop const qualifier (refer to previous commits).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
