Commit graph

24538 commits

Author SHA1 Message Date
Martin Jäger
c56b1dbca1 drivers: can: stm32: rework filter handling
The previous driver implementation aimed to maximize the amount of
filters, which resulted in a fairly complex implementation.

Background: The bxCAN assigns a number to the filters in the order they
appear in the filter banks. This number is used to match messages in
the FIFO with their filter. If the scale or mode of a filter bank is
changed, all following filter numbers get an offset and the assigned
callbacks have to be shifted accordingly.

The required additional space for the shifting operations resulted in
non-deterministic behaviour and the maximum number of filters could not
be determined at compile-time, which made several tests like
tests/drivers/can/api fail.

This implementation uses a more simple but reliable approach for
filtering and and reserves fixed space for extended and standard ID
filters in the available banks (configurable via Kconfig).
The list mode is not used, which may reduce the total number of usable
filters depending on the application.

The maximum amount of filters is 14 if all filters use ext. IDs,
28 if all use std IDs and something in between if mixed IDs are used.

Also see issue #47986 for more detailed background information.

Signed-off-by: Martin Jäger <martin@libre.solar>
2022-08-03 05:02:09 +01:00
Martin Jäger
3524958083 drivers: can: stm32: naming clean-up
Namespace local functions, enums, structs and defines with stm32/STM32
to distinguish them from global CAN API.

Also rename some internal conversion functions to make their meaning
more clear and delete unused defines.

Signed-off-by: Martin Jäger <martin@libre.solar>
2022-08-03 05:02:09 +01:00
Bryce Wilkins
b5a95bad3d drivers: hwinfo: Fix mcux device id
This fixes an issue where the unique device identifier is incorrectly
copied from an address on the AHB bus to memory using memcpy.

I verified corrected behavior by comparing `hwinfo devid` command
output to memory view of the SoC using the debugger.

Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
2022-08-02 13:40:04 -05:00
Fabio Baltieri
24d09d363c include: fix the remaining legacy #include paths
Add the "zephyr/" prefix to various #include statements that are
preventing the CI form running with LEGACY_INCLUDE_PATH=n.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-08-02 16:41:41 +01:00
Kai Vehmanen
0aa116a914 drivers: dai: intel: reduce log clutter in ssp_trigger
With addition of DAI_TRIGGER_COPY, the trigger callback may
be called at a very high rate.

Reduce the logging level from INF to DBG for the logs in
dai_ssp_trigger().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-02 07:11:51 -04:00
Christoph Coenen
81694a25ed segger: Resolve circular include dependencies
Zephyr kernel is dependent on trace.
Trace is dependent on segger rtt.
Segger rtt MUST NOT be dependent on zephyr kernel.

Move lock functions from header into c file to avoid circular
dependency. This fix needs an update of the segger repository.

Fixes #43887.

Signed-off-by: Christoph Coenen <ccoenen@baumer.com>
2022-08-02 13:09:21 +02:00
Kumar Gala
3c35faae36 drivers: ethernet: sam_gmac: Convert to using dts for I2C EEPROM
Introduce a simple binding for atmel,24mac402 EEPROM that the SAM
GMAC ethernet driver can utilize to get MAC address out of.  We
introduce a 'mac-eeprom' phandle into GMAC ethernet devicetree
node that will provide a pointer to the MAC eeprom to utilize.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-02 13:02:42 +02:00
TOKITA Hiroshi
3a1d188a9e drivers: dma: Add GD32 DMA driver
Add support for GD32 DMA

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-08-02 09:13:21 +02:00
Kamil Gawor
e6da6e9133 drivers: bluetooth: hci: Add BT_HAS_HCI_VS selection for RPMSG.
Add explicit selection of the BT_HAS_HCI_VS for
the BT_RPMSG HCI driver. When the HCI over RPMSG
is used this dependency will not be solved automatically.
It is required to handle correctly Bluetooth identity
initialization.

Signed-off-by: Kamil Gawor <Kamil.Gawor@nordicsemi.no>
2022-08-02 09:13:12 +02:00
Gerard Marull-Paretas
3a19948510 drivers: intc: litex: remove machine timer IRQ usage
This platform does not use RISC-V machine timer, however, the interrupt
controller had references to its IRQ. Remove them.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Gerard Marull-Paretas
1c41423210 drivers: timer: riscv_machine_timer: obtain registers/IRQ from DT
Obtain machine timer addresses and IRQ from Devicetree. Note that driver
supports multiple compatibles because mtime/mtimecmp registers are
implemented in different ways depending on the vendor. That means
Devicetree representations can be slightly different and so code to
collect the information needs to treat each compatible differently.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-02 09:12:31 +02:00
Fabio Baltieri
21900c4c33 drivers: sensor: max17055: fix TTE and TTF time units
The unit for SENSOR_CHAN_GAUGE_TIME_TO_EMPTY and
SENSOR_CHAN_GAUGE_TIME_TO_FULL are defined in
zephyr/drivers/sensor.h as being in minutes.

Change the max17055 implementation to match the API spec, fix the
annotation for time register units.

Link: https://datasheets.maximintegrated.com/en/ds/MAX17055.pdf
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-08-01 14:49:59 -05:00
Krzysztof Chruscinski
0f9f18843f drivers: serial: nrfx_uarte: Add workaround for bytes dropping
Add workaround for development kits on which interface chip (segger chip)
is dropping bytes when they are sent in bursts. Issue has been seen on
DK which have multiple virtual com ports on the USB.

A workaround is adding periodic busy waits to introduce gaps in the
transmission.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-08-01 18:06:46 +02:00
David Jablonski
855a489a1c usb_dc_stm32: fix init on soft reset
Soft resetting a STM32 device currently does not reset the USB
connection, which causes a few problems: The endpoints do not respond
anymore, and within zephyr any kind of status information like
CDC_SET_CONTROL_LINE_STATE is also missing as they are not
re-negotiated.

This is fixed by stopping the USB device from zephyr side, right after
initialising the USB device.

Signed-off-by: David Jablonski <dayjaby@gmail.com>
2022-08-01 18:03:42 +02:00
Pieter De Gendt
bef0010e69 drivers: memc: mcux_flexspi: Always try to apply pinctrl state
This commit fixes an issue introduced in 5ee9392 where FlexSPI
pinctrl states where applied based on the SoC type.
However multiple FlexSPI instances can be active, some of which
are not pre-configured from ROM.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-08-01 18:03:10 +02:00
Kumar Gala
84575930f5 i2c: Remove unncessary HAS_I2C_DW Kconfig symbol
The HAS_I2C_DW was to limit Kconfig visibility to only platforms
that utilize the I2C DW IP.  The Kconfig for I2C_DW depends on
DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED which will cause the same
visbility limitation to only platforms that have I2C DW devicetree
nodes.  Thus we can remove HAS_I2C_DW and its references.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-01 18:01:44 +02:00
Caspar Friedrich
ddb1971fe3 drivers: w1: Add driver for Maxim DS2484 Single-Channel 1-Wire Master
This adds a driver for Maxims DS2484 Single-Channel 1-Wire master
driver. The DS2484 features an extra pin to enable sleep modes which
is available if the pin is configured in the device tree.

Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
2022-08-01 10:33:10 +02:00
TOKITA Hiroshi
49522c061f drivers: spi: gd32: support interrupt-driven mode
Add supporting interrupt-based asynchronous operation for GD32 SPI.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-08-01 10:32:33 +02:00
Krzysztof Frydryk
6254274420 ssp: Use sampling rate from config
Use sampling rate passed in config instead of a default one when using
config blob.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-01 10:31:42 +02:00
Conor Paxton
aba67c3329 drivers: gpio: add Microchip PolarFire SoC GPIO driver
This patch adds driver support for Microchip PolarFire
SoC GPIO.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
2022-08-01 10:29:21 +02:00
Jay Vasanth
3e0f738cb2 mec15xx: pinctrl for both mec15xx and mec17xx
Changes to compile pinctrl driver for both mec15xx
and mec17xx. Also add mec15xx pinctrl dtsi

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-08-01 10:28:23 +02:00
Henrik Brix Andersen
aeb9fd68e7 drivers: can: add ESP32 TWAI CAN controller driver
Add ESP32 TWAI CAN controller driver. The TWAI is register-compatible with
the NXP SJA1000 CAN controller.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-07-30 17:32:04 +01:00
Henrik Brix Andersen
491e831436 drivers: can: add NXP SJA1000 common driver backend
Add a common driver backend for NXP SJA1000 compatible CAN controllers.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-07-30 17:32:04 +01:00
Kumar Gala
a529c4511d drivers: flash: Update drivers to use devicetree Kconfig symbol
Update flash drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-30 08:27:13 -05:00
Erwan Gouriou
8325752e27 drivers: clock_control: stm32u5: Get MSIS freq from SoC registers
MSIS frequency at boot time can be different from the one we intent to
set from device tree configuration.
In order to avoid issues, read MSIS configuration from registers to get
the actual freq rather than the devicetree one which may be not yet
configured (which is the case at startup).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-07-30 08:23:35 -05:00
Erwan Gouriou
eb52d8dca2 drivers: clock_control: stm32u5: Switch to HSI only when needed
When configuring PLL, we should first make sure we're not running on PLL,
and if running on PLL, first switch to a fixed clock before proceeding
with PLL configuration.
Current code is doing the switch systematically which is not useful as
default startup case is to use MSI as sysclk source.
So add a test before doing this switch.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-07-30 08:23:35 -05:00
Erwan Gouriou
98e6789cd9 drivers: clock_control: stm32u5: Update condition on PLL1R values
Unlike stated in 57df225b396e43358aac4cc998ed2e99fdb57780, RM0456.pdf
reference manual mentions about PLL1R that "Only division by 1 and even
division factors are allowed."
Though, in reference manual, there is one issue on PLL1R values
description, which should actually be:
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_r_ck = vco1_ck / 4
...
This description will be fixed.

Reflect this in binding and driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-07-30 08:23:35 -05:00
Kumar Gala
0779a932f4 drivers: w1: Update drivers to use devicetree Kconfig symbol
Update w1 drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-29 14:25:27 +02:00
Martin Jäger
c40ec11ab4 drivers: dac: update drivers to use devicetree Kconfig symbol
Update dac drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Martin Jäger <martin@libre.solar>
2022-07-29 14:11:18 +02:00
Sylvio Alves
4120601a6c soc: esp32: allow wifi and net stack into spiram
This PR adds a KConfig option that allows moving
all .noinit content related to wifi a net stack into external
ram. This free dram space to application.

Linker script files are also modified so that the content
are mapped into external ram.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-07-29 14:11:00 +02:00
Jun Lin
ec4f700202 driver: PECI: npcx: add driver support for Nuvoton npcx family
This commit add the PECI driver for Nuvoton npcx family to support PECI
APIs.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-07-29 14:09:17 +02:00
Kumar Gala
dc3e86e7dc drivers: i2c: Update drivers to use devicetree Kconfig symbol
Update i2c drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-28 16:12:43 -05:00
Jun Lin
ed12786ee0 driver: clock_control: npcx: fix the power down of eSPI module
This power down bit of eSPI module is loacted in the bit 7 of PWDWN_CTL6
register rather than the bit 4. This commit fixs the incorrect setting.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-07-28 19:54:34 +01:00
Andrzej Głąbek
e99b323aa2 drivers: pwm_nrfx: Improve tracking of PWM peripheral usage
This is a follow-up to commit 63d6cfd654.

Use a bit mask to store information about channels that need to be
driven by the PWM peripheral instead of inspecting the `seq_values`
array each time.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-07-28 20:52:41 +02:00
Gerard Marull-Paretas
3dd0904ea6 drivers: ieee802154: cmake: remove TI compile definitions
Compile definitions are now injected by the HAL automatically.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:51:55 +02:00
Gerard Marull-Paretas
307415664d soc: riscv: sifive-freedom: remove unused pinmux definitions
These definitions are now part of the pinctrl DT headers, remove them
from soc.h

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-28 20:50:57 +02:00
Kumar Gala
fbc0289733 drivers: bluetooth: hci: spi: Replace DT_INST_LABEL
As we phase out label properties from devicetree the devicetree
node may not have a label so utilize DEVICE_DT_NAME instead
which will use a label if it exists and the node name if not.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-28 20:50:38 +02:00
Anas Nashif
728d8eb2c0 intel_adsp: rename clock registers due to possible conflict
SOF using the same defines and in some cases generating conflicts.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-28 14:11:23 -04:00
Dylan Hung
b374bd0a5d drivers: clock_control: add Aspeed AST10x0 clock control
AST10x0 series SOCs provide the clock controller through the syscon
hardware block.  The current driver supports the clock gating capability
for the hardware IPs embedded in the SOC.  Each clock source has a
clock ID that can simply map to a bit in syscon registers CLK_STOP_CTRL0
(group 0) or CLK_STOP_CTRL1 (group 1).  There are some clock sources
that don't have associated clock gating control, which are always on,
are grouped to into group 2.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-07-28 08:30:27 +02:00
Andrzej Głąbek
d5222f318d drivers: pwm_nrfx: Fix PWM_NRFX_CH_VALUE() macro
This is a follow-up to commit 63d6cfd654.

Revert unwanted PWM_NRFX_CH_POLARITY_MASK to PWM_NRFX_CH_COMPARE_MASK
replacement that was accidentally done in the above commit.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-07-27 17:03:38 +00:00
Francois Ramu
b165f10795 drivers: flash: octospi drivers for stm32h7 serie
With the introduction of the OSPI NOR flash controller
the stm32H7 serie requires the HAL MDMA in anycase.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-27 18:46:25 +02:00
Andreas Sandberg
61306aedb4 drivers: ssd16xx: Add an API to read raw RAM contents
Add the ssd16xx_read_ram() function that can be used to read the raw
contents of the two display RAM in the controller. This function is
similar to display_read(), but lets the caller specify the RAM to
operate on. The intention is that this can be used to read out the
contents of the old frame buffer after a partial refresh that
automatically swaps the black/red buffers.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:47 +02:00
Andreas Sandberg
8312db7734 drivers: ssd16xx: Implement basic read support
Read operations only work on SPI controllers that support half
duplex. To enable read operations, set the device mode to half duplex
by adding the following to the device's DTB node:

  duplex = <SPI_HALF_DUPLEX>;

If read requests will fail with -ENOTSUP if the device isn't in half
duplex mode.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:47 +02:00
Andreas Sandberg
25cff5edc3 drivers: uc81xx: Avoid using auto sequencing
The UC8179 supports automatic power management where the DC-DC is
enabled automatically. This is not supported on the UC8176. Explicitly
call PON/DRF/POF from uc81xx_update_display instead. This ensures that
the DC-DC is only enabled while actually updating the display for all
supported chips.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:02 +02:00
Andreas Sandberg
f4a6c75087 drivers: uc81xx: Fix incorrect UC8176 CDI layout
The CDI register in UC8176 and UC8179 have different layouts. Add a
helper function to the quirks structure to handle CDI updates.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:02 +02:00
Andreas Sandberg
f6bbbc3c7d drivers: uc81xx: Use device-specific compatibles
The UC8176 and UC8179 chips that exist in tree have subtly different
register layouts. Use separate compatible strings for these chips and
a quirks structure that describe device-specific behavior.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:02 +02:00
Andreas Sandberg
8f0093aaf8 drivers: Rename GD7965 to UC81xx
The GD7965 driver is really just a vendor name for the UltraChip
UC8179. Rename the driver to UC81xx since there are other chips in the
family (e.g., the UC8176) with an almost identical register interface.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-27 18:45:02 +02:00
Thomas Stranger
0d7abdf012 drivers/clock_control: stm32 common fix STM32_SRC_PLLCLK calculation
Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.

This commit resolves this issue for l0, l1.

get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-07-27 18:44:49 +02:00
Glauber Maroto Ferreira
dbbfcfc22d esp32: driver: counter: add RTC-based implementation
add RTC-based implementation of the counter driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-27 09:48:33 +02:00
Kumar Gala
47bb8c14dc drivers: clock_control: Update drivers to use devicetree Kconfig symbol
Update clock_control drivers to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 09:47:16 +02:00