In some case the structure enclosing the adc context
can be quite big, making static initialization quite
resource consuming
Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
Enabling the FlexSPI HyperRAM results in a build error, due to a logging
module re-definition. Fixed by changing the log module name.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
increase available RX buffers to MCUX ethernet driver.
improves measured performance on RT1050 EVK zperf download
from 500Kbps to 22Mbps.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch extends the adxl362 driver by adding an option
to change the inactivity detection timeout at runtime.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Building lwm2m_client with CONFIG_NET_L2_OPENTHREAD=y leads to
following warning during build:
west build -s samples/net/lwm2m_client -b nrf52840dk_nrf52840 -- \
-DCONFIG_NET_L2_OPENTHREAD=y
zephyr/drivers/sensor/nrf5/temp_nrf5.c:115:10:
warning: zero-length gnu_printf format string [-Wformat-zero-length]
115 | LOG_DBG("");
Signed-off-by: Kiril Petrov <retfie@gmail.com>
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use logical values of 0/1 for gpio_pin_set_dt and handle any
inversions as GPIO flags that might be required at a board level.
Signed-off-by: Kumar Gala <galak@kernel.org>
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When using the settings subsystem, the data argument argument passed to
flash_stm32_write_range() might not be 8-bytes aligned, causing an
unaligned memory access fault.
Fix that the same way as it was done for the STM32L4 in commit
652efa530f.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Now that we have 8 bits reserved for vendor specific GPIO flags,
introduce a new set of flags for nRF platforms to configure pins drive
mode. These new flags are equivalent to the previous existing ones, but
use a naming scheme the fits better with vendor hardware capabilities.
The table below shows the equivalence between old and new flag
| Old flags | New flags |
|---------------------------|-----------------------|
| `NRF_GPIO_DS_DFLT_LOW` | `NRF_GPIO_DRIVE_S0` |
| `NRF_GPIO_DS_DFLT_HIGH` | `NRF_GPIO_DRIVE_S1` |
| `NRF_GPIO_DS_ALT_LOW` | `NRF_GPIO_DRIVE_H0` |
| `NRF_GPIO_DS_ALT_HIGH` | `NRF_GPIO_DRIVE_H1` |
| `NRF_GPIO_DS_DFLT` | `NRF_GPIO_DRIVE_S0S1` |
| `NRF_GPIO_DS_ALT` | `NRF_GPIO_DRIVE_H0H1` |
| `NRF_GPIO_DS_DFLT_LOW \|` | `NRF_GPIO_DRIVE_S0H1` |
| `NRF_GPIO_DS_ALT_HIGH` | |
| `NRF_GPIO_DS_ALT_LOW \|` | `NRF_GPIO_DRIVE_H0S1` |
| `NRF_GPIO_DS_DFLT_HIGH` | |
Documentation has been written to explain in more detail the meaning of
the flags and how they can be used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The naming of the custom DS flags is not clear for nRF platforms. This
patch removes all the NRF_GPIO_DS* flags. New flags will be
re-introduced in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit avoid re-enabling the ADC,
because this starts conversion.
According to the RefMan (RM0008) of the stm32F10x mcu,
enabling the ADC will start the conversion
if the ADC is already enabled. "Conversion starts when
this bit holds a value of 1 and a 1 is written to it."
That's not what we want.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
When using the APIC imer in TSC deadline mode, also enable reading the
full 64-bit cycle counter value (via the k_cycle_get_64() call).
Signed-off-by: Bruno Achauer <bruno.achauer@intel.com>
When PINCTRL is enabled, the SCL and SDA pin numbers are not available
in configuration structures used for nrfx drivers initialization.
In this case, these pin numbers need to be obtained from peripheral
registers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Not all platforms support setting the LSE driving capability, causing
the build to fail for platform such as the STM32L072 if compiled with
CONFIG_STM32_LPTIM_CLOCK_LSE=y.
Adding an #ifdef guard around the call to skip it if not defined in the
HAL.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
In npcx series, not all GPIO pads support Multi-Input Wake-Up Unit
(MIWU) functionality. Hence, this CL adds checking whether GPIO's pad
configuration is valid first before using it.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Simplify the implementation by using gpio_dt_spec. Mostly
gpio_dt_spec is used as a common struct and lets us move
away from DT_INST_GPIO_LABEL.
Signed-off-by: Kumar Gala <galak@kernel.org>
Some stm32 devices, like stm32F4, do not have
a PLL Enable bit on the PLLP nor PLLQ divider
in their PLL config register (PLLCFGR).
The result is a empty function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The function get_pllsrc_frequency is added
with possible source HSI or HSE.
With STM32_PLL_P_ENABLED or STM32_PLL_Q_ENABLED,
this function is used by the clock control driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.
This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
The hwinfo shell commands was missing human readable names for
* RESET_HARDWARE
* RESET_USER
* RESET_TEMPERATURE
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This peripheral combines a hardware-based USB CDC ACM serial interface
and a JTAG interface.
It is present in the ESP32-C3.
Signed-off-by: Martin Jäger <martin@libre.solar>
The uart_pipe driver is not dependent on any console driver,
however a serial driver is required.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Add timer driver based on CAVS driver and adapted for Meteor Lake.
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add TLB driver specific for Meteorlake.
Add missing kconfig resource and fix include path
add hpsram power up and ref counter
Use memblock to track physical page usage in mtl tlb driver. The
applications that will be using the tlb memory driver should not
track the physical page mapping to virtual address space:
- adds an option to use the phys argument value of 0 to tell the
driver to autonomously assign physical pages upon map request
- makes the tlb driver use memblock to track mapped physical pages
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Co-authored-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
