This is currently the only end-point where multiple threads can access
the NVMe device (all calls are synchronous).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Pre-allocating PRP list for such purpose. Which PRP list is relevantly
filled in depending on the data size and data pointer page alignment.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
Namespace in this context, will be a disk. It's not exposed from DTS, as
an actualy NVMe hardware controller card can bring more than one
namespace (disk).
Thus namespace are not instanciated through the device driver model, but
statically allocated and runtime configured, depending on what the
controller exposes.
By default the amount of namespace supported is one as it is the most
common setup.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
This is the corner stone of the whole NVMe logic: sending commands and
getting replies, all through memory shared from the host to the
controller.
Then using it to inialize admit/IO queues and identifying the
controller.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
Since Zephyr does not propose any advanced interfaces as FreeBSD (bus
abstractions, memory and DMA abstraction and many more), this comes with
a much simplified and Zephyr-ish way to instanciate, initialize and use
NVMe controller.
ToDo: IO Queues cannot be more than 1. Macros will need to be improved to
manage the case of 2+ IO queues.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no event reporting WiFi disconnect, create a polling
work for this and report the event.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
It has been observed that sockets can be in bad state after
boot. Be sure to correctly reset local port and any 'server'
mode before configuring client mode.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
- We should wait indefinitely if msecs is -1 (FOREVER).
- We can directly return if data is already available in FIFO.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
There is no listen or accept for UDP, we need to enable the UDP
server mode (P5=1) as soon as bind is complete.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The implementation of GIC v3 ITS uses k_aligned_malloc(), which will
only work if dynamic memory is available (system heap). Tell the user
that a dynamic memory pool is required.
The amount of memory will depend on registers probed during runtime.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
CFG register uses fields that are not defined in Synopsys databook of
Designware AHB DMA Controller.
Since current Zephyr code uses this driver only for the
intel_adsp_gpdma driver I assume that those fields are specific to
this DMA which is not the standard Designware one.
This patch allows to use either the standard Designware register or
the Intel one.
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
There is no need to use *_cmp_raw() functions here, all they do is cast the
pointers to in(6)_addr* and call the non-raw functions. Additionally, this
fixes a warning for the net_ipv6_addr_cmp_raw() call, which didn't cast the
arguments correctly.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Syntacore RISC-V platforms have dedicated MTIMER_DIVIDER register which
should be configured during the Timer initialization.
The configuration of dedicated MTIMER_DIVIDER register could now
be performed during initialization if its address is provided.
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
This change adds a mutex to protect against simultaneous access to the bus
instead of returning an error during transfers. Since most I2C code doesn't
handle retries (especially with a -EIO code) not blocking on a mutex can
cause a number of problems.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
move DT_DRV_COMPAT to bmp388.h. so that can be decide which
interface to use.
define struct bmp388_bus_io interface bmp388_i2c.c and bmp388_spi.c.
redefined bus operation interface in bmp388.c, this allow the driver
to decide which interface to use during construction
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
This adds support for the -02 variant, as well as the existing -30.
The sensor type is automatically read from configuration register at
device init, an appropriate compensation func is set up
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
This adds a driver for the DS2482-800 1-wire multi channel bus driver.
The driver uses a split architecture in order to share a common lock
among all configured channels of a single IC.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
ds248x no longer applies to all drivers. Therefore the naming indicates
compatibility with DS2482 and DS2484 drivers.
Also
- Fix some code formatting
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
With the stm32h5x, hal driver is xspi for octospi
Add a header file to map functions and constants.
The ospi driver of the stm32H5x serie does not support DMA yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Implement the driver method pin_interrupt_enable and pin_interrupt_disable.
This commit fixes getting the get_pending_int by updating the interrupts
field in the gpio_emul_data filed when interrupt is triggered. Also,
introduces a new filed enabled_interrupts to better simulate the
behavior of the interrupt pending and whether the interrupt is
enabled/disabled.
Signed-off-by: Sung-Chi Li <lschyi@google.com>
Add pin_interrupt_enable and pin_interrupt_disable in gpio_driver_api,
and add corresponding APIs in gpio.h for application to enable/disable
an interrupt without reconfiguring again.
This CL also Create a new Kconfig option for this feature.
Signed-off-by: Sung-Chi Li <lschyi@google.com>
Use the LTDC in combination with the DSI HOST makes the pinctrl obsolete.
DSI HOST has dedicated pins.
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
Ignore the link clock_source for non-ACE platforms instead of throwing
an error when it is set in the topology.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
We need to ensure that the XEC GIRQs are initialized after the
XEC ECIA device. Right now we depend on the linker ordering
things correctly since everything is at INTC_INIT_PRIORITY
priority
Set the XEC GIRQs to 41 so the init priority is one more than
INTC_INIT_PRIORITY that is used by xec-ecia.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Added support for async APIs for ns16550. This will be
enabled by kconfig CONFIG_UART_ASYNC_API.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
There have an extral TBE interrupt event though we have cleared the
SPI_CTL1_TBEIE bit. To cover this situation, add a on_going check
before enter exchange function.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Add the stm32h5 serie to the stm32 RTC counter driver
EXTI Line is 17 (for stm32h50x or non-secure stm32h56x/h57x).
The drivers must Enable access to the BackUp Domain.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This case takes a float value and passes it to the integer abs function,
storing the result in an integer type variable. That looks like a possible
error to clang, so insert an explicit cast to int to make the compiler
happy.
Signed-off-by: Keith Packard <keithp@keithp.com>
With this patch DMIC device after init will be in OFF state. When power
domain will be powered-up device will switch into suspended state and
change it to active only when is used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Since the device need to be first powered-up by the power domain, it has
more sense that device is in off state at the beginning.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
