Commit graph

24538 commits

Author SHA1 Message Date
Johann Fischer
ac649c35fd drivers: udc: add driver for virtual USB device controller
Add support for virtual USB device controller intended for use
by virtual bus and virtual UHC controllers. This driver is not
an emulation of any real host controller.
The driver has initial support for handling control and bulk
transfers.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-12-16 13:21:12 +01:00
Johann Fischer
deb637eb8a drivers: usb: add support for virtual USB bus
Add support for virtual USB bus (UVB) intended for use
by virtual UDC and UHC controllers. UVB is not an emulation
of the USB bus or protocol but a simplified service to connect
a virtual host controller to one or more virtual device
controllers.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-12-16 13:21:12 +01:00
Johann Fischer
da639954c1 drivers: usb: add common layer of UHC API and MAX3421E driver
Add common layer of UHC API and MAX3421E host controller driver.
This implements the bare minimum necessary to communicate with
one peripheral device.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-12-16 13:21:12 +01:00
Tomasz Leman
af6d827b64 drivers: hda: enable runtime power mgmt in intel hda dma
Enable Zephyr device runtime power management mechanisms in Intel HDA
DMA driver. This allows Zephyr to track usage reference for power domain
gating.

PM action handler is currently empty and will be fill out later.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-16 11:03:15 +00:00
Gerard Marull-Paretas
7568749c8c drivers: regulator: initial driver for nPM6001
Add initial driver for the nPM6001 PMIC.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-16 11:26:47 +01:00
Daniel DeGrasse
4be1fb81ce soc: arm: nxp: switch imxrt boards to use systick timer unless CONFIG_PM=y
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-16 09:31:48 +01:00
Tomasz Leman
de1bd1fa04 drivers: gpdma: enable runtime power mgmt in intel gpdma
Enable Zephyr device runtime power management mechanisms in Intel GP DMA
driver. This allows Zephyr to track usage reference for power domain
gating.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-15 19:17:21 +01:00
Marek Matej
45d55205db drivers: esp32: temp: CPU die temperature sensor
Support for the measuring the CPU die temperature
for the ESP32 targets S2,C3. The ESP32 support
was ommited due to lack of offset calibration.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2022-12-15 18:21:39 +01:00
Cyril Fougeray
00ceb258d3 drivers: flash: clear stm32 status register errors
In case of errors in the status register and to
unblock Flash, it is advised to clear the errors.

Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
2022-12-15 14:31:37 +00:00
Ryan McClelland
1f489cf03a drivers: usb: stm32: add usb hs ulpi support
Add support for the STM32H7 USB OTG HS and support for the ULPI PHY.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2022-12-15 14:28:00 +00:00
Dinesh Kumar K
f050e18798 drivers: sensor: Add support for grow_r502a fingerprint sensor
Add driver support for grow_r502a fingerprint sensor

Signed-off-by: Dinesh Kumar K <dinesh@linumiz.com>
2022-12-14 18:44:29 +01:00
Gerard Marull-Paretas
539d4aa6e6 drivers: regulator: add common init enable API
Add a new API for drivers that can be called to initialize the regulator
at init time if `regulator-boot-on` or `regulator-always-on` are set.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
9b5152153b drivers: regulator: add regulator_is_enabled
Add a new API to check if a regulator is enabled or not.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
305ce33b77 drivers: regulator: add parent DVS API
PCA9420 PMIC offers of multiple operation states, or DVS (Dynamic
Voltage Scaling). Such states may be automatically changed by hardware
using MODESEL0/1 pins. Certain MCUs allow to automatically configure
certain output pins when entering low power modes so that PMIC state is
changed without software intervention.  This means that application just
needs to configure the voltages for each state using
`nxp,modeN-microvolt`, set `nxp,enable-modesel-pins` in devicetree and
forget about configuring regulators.

This patch introduces a new _parent_ API to expose such functionality in
a vendor agnostic way. Consider this API as experimental for now, until
we have other usecases.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
10ce9684c3 drivers: regulator: fix/improve usage of devicetree properties
Most of devicetree properties for regulator, such as:

- regulator-min/max-microvolt
- regulator-min/max-microamp
- regulator-allowed-modes
- etc.

Are meant to specify limits on what consumers may set. They are **NOT**
meant to describe the hardware capabilities. For example, I could have a
BUCK converter that supports 0-5V output voltage, but my circuit may
only allow working on the 2.7-3.3V range.

This patch reworks the API so that the API class layer manages this
information. This is done by drivers collecting all such fields in a
common configuration structure that is later accessed by the class
layer. This simplifies drivers implementation. For example, if A
consumer calls regulator_set_voltage() with a voltage that is supported
but not allowed, driver code won't be called. Similarly, if a regulator
is configured to be `always-on`, enable/disable driver code will never
be called.

Drivers have been adjusted. PCA9420 mode settings have been removed from
devicetree in this commit as they are not actual modes but PMIC states.
This will be refactored in a follow-up commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
1029a4db6f drivers: regulator: pca9420: some minor improvements
- Remove redundant comments
- Remove internal *_mode functions, as they were only used once.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
8e60c2df0c drivers: regulator: add regulator_mode_t opaque type
Define regulator mode as an opaque type, same as we do in other
subsystems like GPIO (e.g. gpio_flags_t).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
2bd6d50934 drivers: regulator: improve regulator_get_current_limit
- Function returns now the value by reference, similar to voltage
  counterparts.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
8db7e046c5 drivers: regulator: clarify regulator_set_mode interface
Clarify the API for regulators that have the option to set mode
externally, such as PCA9420. Adjust the PCA9420 driver to comply with
the interface.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
3d47b6dfba drivers: regulator: improve regulator_get_voltage
- Function now returns error, value is obtained by reference. This
  allows to propagate potential bus errors.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
b909d0e560 drivers: regulator: drop mode specific APIs
- Mode specific APIs repeat the same functionality offered by non-mode
  specific APIs
- The same functionality can be achieved by the non-mode APIs, since
  they apply to the active mode which can be set using
  regulator_set_mode() first.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
4e8795a8ce drivers: regulator: provide generic regulator_is_supported_voltage
The function can be implemented by using regulator_count_voltages() +
regulator_list_voltage(), so there's no need to defer the job to each
driver.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
c77c3ac7d6 drivers: regulator: improve regulator_list_voltages
- Rename to regulator_list_voltage (it is listing a single voltage)
- Function returns the value via a parameters, so that we can indicate
  wether the given index is valid or not. If a driver doesn't implement
  this call, function returns -EINVAL (as it should be).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
aab28d735f drivers: regulator: drop regulator_count_modes
The regulator_count_modes was an API that was not useful. Unlike with
voltages where the interface guarantees they are zero-indexed, modes can
take an arbitrary identifier. So counting supported modes doesn't
provide any useful information such as if a mode is allowed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Gerard Marull-Paretas
9a73be82c4 drivers: regulator: improve regulator_count_voltages specs
- Interface guarantees that voltage indices start from zero to
  regulator_count_voltages()
- Function always return an unsigned number. If the device doesn't
  implement the API returned value is zero, as expected.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-14 17:01:44 +01:00
Johann Fischer
95717520bf drivers: udc: do not call driver's dequeue on empty fifo
Do not call driver's dequeue implementation if endpoint fifo
is empty.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-12-14 12:06:03 +01:00
Johann Fischer
721b8c22d8 drivers: udc_nrf: dequeue instantly when endpoint is not busy
In the case that IN endpoint is not busy there will be
no notification from the HAL driver.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-12-14 12:06:03 +01:00
Michal Moskal
d46b9bd124 drivers: hwinfo: Implement hwinfo_get_device_id for ESP32-C3
ESP32-C3 uses different fuse addresses for storing the MAC addr,
but the the format is the same.

Signed-off-by: Michal Moskal <michal@moskal.me>
2022-12-14 09:51:44 +01:00
Tom Burdick
603cc27045 dma: Add max block count attribute
Adds an attribute that describes the maximum number of scatter gather
blocks that the DMA will accept. Useful in cases where DMA is used as
the abstraction for moving data around (e.g. SoF audio streams) and
variances of the hardware need to inform decisions about how to use
the DMA API.

Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Co-authored-by: Jaska Uimonen <jaska.uimonen@intel.com>
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-12-14 09:51:10 +01:00
Marek Matej
f86a7d2c25 drivers: dac: esp32: Add support for DAC controller
Initial DAC driver for the ESP32/ESP32-S2 SOCs

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2022-12-13 16:29:38 +00:00
Aaron Massey
5e33f833ed fuel_gauge: Fix sbs_gauge err to conform to API
The SBS fuel gauge driver did not return a count of the number of
properties that failed.

Fix this and add a test that verifies the sbs_gauge returns the number of
failing properties as well as a test that verifies a negative return code
if all properties failed.

Signed-off-by: Aaron Massey <aaronmassey@google.com>
2022-12-13 11:10:44 +01:00
Huifeng Zhang
12fa8335a3 drivers: gicv3: add zephyr kernel header file
zephyr kernel header file should be included otherwise gcc will report
the warning: implicit declaration of function 'k_aligned_alloc' and
the return value of 'k_aligned_alloc' will be treated as an int type,
which will cause an error on the 64 bits platform.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2022-12-13 18:08:40 +09:00
Ryan McClelland
672a401f20 i3c: add cdns i3c driver
This gives initial support to the cadence i3c controller

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2022-12-12 15:51:16 -05:00
Ryan McClelland
371470d608 i3c: GETMWL and GETMRL may be optionally supported if no settable limit
According to section 5.1.9.3.5 and 5.1.9.3.6 of the I3C Specification
v1.1.1. This CCC is may be optionally supported if the target device
has no settable limit.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2022-12-12 15:51:16 -05:00
Ryan McClelland
b7dc01cd48 i3c: rename is_primary to is_secondary
Rename is_primary to is_secondary. The justification for this is
because it is less likely to have something configured to be
secondary, and the 0 value would be if it is primary.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2022-12-12 15:51:16 -05:00
Erwan Gouriou
428700f709 drivers: gpio: stm32: Keep port clock in input configuration
When pin is configured in input mode, clock is also required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-12-12 15:50:21 -05:00
Ravik Hasija
22e2b004df drivers: serial: Add Driver for CDNS UART IP6528
Adding New Serial/UART driver for Cadence UART IP6528.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-12 12:19:35 -05:00
Marco Argiolas
3540ae1df9 drivers: sensor: bmm150: fix mispelling
Build error appearing only when enabling CONFIG_BMM150_PRESET_LOW_POWER

Signed-off-by: Marco Argiolas <marco.argiolas@ftpsolutions.com.au>
2022-12-12 10:54:40 -06:00
Brian Dunlay
491933b185 drivers: wifi: eswifi: Guard net_ctx state change
Previously, a call to set the net_context state was added here to
accommodate a new KConfig scenario that permitted disabling offload
sockets. This code path is used by both local and offloaded sockets.
While it is necessary to update the state of the net_context for a
locally managed socket, setting the net_context for an offloaded socket
is an error, as the net_context is invalid (in fact, it points to a
hard-coded dummy socket), as observed in #52346 and #38544.

A prior commit (a9ac0a88) attempting to remedy the offload socket
scenario removed this line, which resulted in problems for the local
socket scenario. The socket never got updated to the connected state,
and thus was unusable.

Adding this guard allows the eswifi socket to set the socket net_context
only if the socket is NOT offloaded.

Signed-off-by: Brian Dunlay <brian@nubix.io>
2022-12-12 14:55:03 +01:00
Andriy Gelman
a9481bdbe1 drivers: gpio_xmc4xxx: Use interrupt controller for edge/level interrupts
Use the XMC4XXX interrupt controller for edge/level gpio interrupts.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
Andriy Gelman
727e589448 drivers: interrupt_controller: Add XMC4XXX ERU driver
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.

This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.

The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
Duong Vu Nam
b24f4625f0 arch: support nocache for Cortex-R52
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
TOKITA Hiroshi
e965db984d samples: counter: alarm: add support for GD32 boards
Add support for boards that implements the GD32 SoCs.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi
981d88bf7b drivers: counter: add support for GD32 timer
Adds support for GD32 timer

Note: Currently, it is not supporting RISC-V(GD32V) devices.
It needs some work on the interrupt controller first.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi
d38a1fe2fa drivers: clock_control: gd32: timer should recognize with entire id
The timer_ids contain timers that belong to any bus.
So, It should recognize with entire id, not only the CLOCK_ID_BIT part.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi
79451c221a drivers: clock_control: gd32: Correcting timer node detection
DT_COMPAT_GET_ANY_STATUS_OKAY is not suited for the node's existing check.
(This macro returns the stem of the DTS macro name,
 the stem part is not a defined symbol.)
Instead, it should use the DT_HAS_COMPAT_STATUS_OKAY macro.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
Ravik Hasija
96da6f2234 driver: dw: Use base_addr variable to set dir.
Change Summary:
Update Base addr to set direction to use Aligned IP base address instead
of Port Base Address. Port Base Address + offset to direction register
will set incorrect value for Port B,C & D. For ex: In cases when more than
1 port is configured on the same IP, the DTS node for port B will start
at offset 0xC. Calculating the port using Port Base will yield offset of
PORTB DIR register which is at offset 0x10 from Aligned Base, and as a
result will result in setting DIR register of PORTC instead.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-11 20:37:33 -05:00
Ravik Hasija
7ba1925d97 driver: gpio: Fixing Pin Direction Setting.
Change Summary:
Moving the setting of Pin direction before setting/clearing the pin
configured as output for the change to correctly take place.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-11 20:37:33 -05:00
Rodrigo Cataldo
bcb3961567 drivers: pcie: late initialization of pcie when PCIe controller is used
For architectures that rely on a PCIe controller (for example, ARM64),
scanning the PCI space will only succeed after the controller has
initialized. Therefore, in the presence of PCIe controller, the PCIe
initialization is bumped to the next system init level.

In the past, drivers like ivshmem would do a late scan of the PCI space
in case the early scan failed; however, the cited commit removed this
feature and ivshmem fails for ARM64. This commit fix this by making the
early scan succeed.

Fixes: a96016d747 ("drivers: ivshmem: Remove unnecessary BDF lookup ...")
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2022-12-10 09:47:26 +01:00
Rodrigo Cataldo
0efb0f55b3 drivers: ivshmem: msi.h header only required for ivshmem-doorbell
Only include the MSI header when ivshmem-doorbell is employed, as the
ivshmem data structures already use the same protection for msi-related
structures.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2022-12-10 09:47:26 +01:00