Update LPSS DMA init interface which is common and
independent of parent-node.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
We should set the z_clock_hw_cycles_per_sec as the value of
the system clock frequency.
There was a mistake in referencing the clock source set before
initialization.
I corrected it to reflect the clock value after initialization.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
I/O or memory decoding should be disabled via the command register
before sizing BAR for calculation MMIO size
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Only copy up to IFNAMSIZ - 1 number of characters of the interface name to
leave room for null termination of string.
Fixes: #66777
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
When reconfiguring a previously used endpoint, it may still be locked
when a write was taking place when e.g. the host application crashed.
The call to udc_rpi_cancel_endpoint seems to do a proper cleanup of
the endpoint, i.e. the write semaphore will be released.
Fixes#66723.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
When Bluetooth is enabled, it is required to arbitrate flash accesses
between RF and write accesses (for user activity).
A dedicated flash manager is provided as part of STM32WBA BLE lib.
Implement a dedicated driver using FM Apis to handle RF activity.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32WBA controller uses a PKA driver to perform cyphering operations
on keys. Since PKA hardware block requires RNG clock to be enabled, a
synchronization with zephyr RNG driver is needed.
Use RNG enable status to check if RNG could be switched off or needs to
be switched on.
Similarly in entropy driver, don't cut RNG clock if PKA is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The driver works on active low signals only, change the interrupt
configuration to trigger on falling edges only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
There are some issues with the extended endpoint settings. The incorrect
setting leads to the chip being unable to respond with NAK when the host
polls the extended endpoint for data transfers. Additionally, the controls
for the extended endpoint's ISO and PID data sequence are also incorrect.
This commit addresses these issues to properly support extended endpoint
transactions.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are two registers that control the selection of one FIFO as data
buffer for 15 endpoints (ep1-ep15). Both registers should be configured
before sending and receiving data. Additionally, there was an issue with
the corresponding FIFO index setting in the 'usb_dc_ep_read_continue'
function, which has been addressed in this commit.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Turning on clock via clock controller and
resetting PIO device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Turning on clock via clock controller and
resetting PIO device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Turning on clock via clock controller and
resetting ADC device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changed how to get clock frequency for PL022
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Removed all function calls from Raspberry Pi Pico SDK
Added functions for setting uart baudrate and format
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changed how to get xtal frequency for Raspberry Pi Pico
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The stm32H5 mcu has an independent USB supply to be enabled
at init with LL_PWR_EnableVDDUSB function like the stm32U5 serie.
Both series have PWR_USBSCR_USB33SV bit in their USBSCR POWER reg.
and other series all have PWR_CR2_USV bit in their CR2 POWER reg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Boot into the deep power down state when `SPI_NOR_IDLE_IN_DPD` is not
enabled. DPD is the correct hardware state for the `SUSPENDED` software
state. Without this change, it takes a cycle of
`SUSPENDED->ACTIVE->SUSPENDED` to get to the low power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The previous behaviour led to an issue where we already expected data1
on the first transfer instead of data0. The DesignWare USB DC actually
implements the same behaviour. Also, the next_pid flag has to be reset
on setting up the endpoint.
Fixes#66283.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
The driver right now re-enters polling mode a couple times after the
matrix has been detected as stable as the key interrupt is still pending
and fires again once detection is reenabled.
Clear pending WUI interrupts before reenabling key press detection to
avoid that.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Information about IOAPIC can be located not in the first
DMAR Hardware Unit Definition subtable. Iterate them all.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Fixes uninitialized variable return by returning zero
at the end of function.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This code fixes following issue:
The TX data chunk (with NORX set) is send to chip (via SPI) and at the
same time a frame is received (by the LAN8651 chip), there will be no IRQ
(the CS is still asserted), just the footer will indicate this with the
rca > 0.
Afterwards, new frames are received by LAN865x, but as the previous footer
already is larger than zero there is no IRQ generated.
To be more specific (from [1], chapter 7.7):
----->8-------
RCA – Receive Chunks Available
Asserted:
The MAC-PHY detects CSn deasserted and the previous data footer had no
receive data chunks available (RCA = 0). The IRQn pin will be asserted
when receive data chunks become available for reading while CSn is
deasserted.
Deasserted:
On reception of the first data header following CSn being asserted
------8<------
Doc:
[1] - "OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface"
OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The description is a bit misleading as the packet is not even read in
the mentioned case by the OA TC6 Zephyr driver.
When the timeout occurs the data (packet) received by LAN865x may be:
- Read latter if still in the RX buffer of LAN865x
or
- Is (probably) dropped by LAN8651 itself as the RX buffer gets overrun
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The parity of the received footer from data transfer (also including the
NORX) shall be checked before members of struct tc6 are updated.
This prevents from updating the driver's crucial metadata (i.e. struct
oa_tc6) with malformed values and informs the upper layers of the driver
that error has been detected.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the current approach, the driver prevents from TX transmission
when waiting on timeout (standard 100ms) for available memory to be
able to allocate memory for RX packet.
It is safe to just protect the part of reading chunks. In that way
pending TX transmission can be performed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If the DT node for mdio of nxp enet has a mdc freq specified,
use this when configuring the module.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
In init function, start timer with period CYC_PER_TICK if tickless is
not enabled, This change is for fixing the issue that disabling
CONFIG_TICKLESS_KERNEL the OS tick is not work issue, this
causes the OS not starting scheduling correctly.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
