When usb middleware sends a start of frame notification to this driver,
call status_cb with USB_DC_SOF.
Signed-off-by: James Zipperer <jzipperer@fb.com>
Add an input driver to read data from an analog device, such as a
thumbstick, connected to an ADC channel, and report it as an input
device.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver that based on RPI-PICO's PIO feature for ws2812.
This driver can handle WS2812 or compatible LED strips.
The single PIO node can handle up to 4 strips.
Any pins that can be configured for PIO can be used for strips.
I verified the samples/driver/led_ws2812 sample
working with WS2812(144 pcs) led strip using following patches.
- samples/drivers/led_ws2812/boards/rpi_pico.overlay
```
/ {
aliases {
led-strip = &ws2812;
};
};
&pinctrl {
ws2812_pio0_default: ws2812_pio0_default {
ws2812 {
pinmux = <PIO0_P21>;
};
};
};
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
ws2812: ws2812 {
status = "okay";
output-pin = <21>;
chain-length = <144>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
```
- samples/drivers/led_ws2812/boards/rpi_pico.conf
```
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use proper register mask for software reset register so
reset magic value sent to device is not malformed.
Co-authored-by: Bartosz Bilas <b.bilas@grinn-global.com>
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
While waiting for the UART to be ready in ISR
mode, for simulation only, add a tiny delay per
iteration of the busy wait loops to allow
time to pass.
This Z_SPIN_DELAY is an empty macro for any
other target than simulation.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Instead of getting the hardcoded address from the DT structure
use its symbolic name which will be resolved by the nRF HAL
definitions to the same value.
This allows the TIMER peripherals' addresses to be redefined
for the simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The ISR prototype is not matching the
signature for interrupt handlers, which results in
build warnings.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
For simulation, we cannot get the UART regiter address
for the pinctrl config structure from DT, as that
cannot match the one allocated at build time.
So let's override it at runtime with the correct address
which is stored in the UART config structure.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Instead of getting the hardcoded address from the DT structure
use its symbolic name which will be resolved by the nRF HAL
definitions to the same value.
This allows the GPIO peripherals' addresses to be redefined
for the simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The ISR prototype used when building without the
interrupt driven UART was not matching the
signature for interrupt handlers, which results in
build warnings.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Interrupt trigger type register each bit indicate the configured interrupt
type. bit value is 0 indicate level trigger interrupt, 1 indicate edge
trigger interrupt.
The level trigger defined to ~BIT(0) equal 0xfffffffe not equal 0.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
A Zero Length Packet can be used by higher layer stack to discover when
an endpoint is being processed by the host. An example of this was
introduced as part of 0127d000a2 ("usb: device: cdc_acm: Use ZLP to
detect initial host read") in the CDC ACM class.
Not invoking the callback for ZLPs results in the higher layer stack not
being informed when the packet is consumed. This manifests as a CDC ACM
USB-IP device that cannot transmit to the host while being able to
receive from the host.
Signed-off-by: Abe Kohandel <abe.kohandel@gmail.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit partially reverts a change which was introduced in the
previous commit 5b9a0e5456.
usb_dc_ep_start_read() should also be called on transfer endpoints
like it has been before, otherwise the endpoint will not be armed
after it has been reconfigured.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
... so that it is possible to use a GPIO expander pin as the CS line.
Communication with the expander may involve an operation that cannot
be done from the interrupt context (e.g. an I2C transaction).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit ea1be7f242.
After the driver performs its initialization, it needs to deactivate
the QSPI peripheral. Otherwise, the peripheral would unnecessarily
consume power until some QSPI operation is performed (and only then
it will get deactivated), what depending on the application may take
a significant amount of time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
`release` is a mandatory method in the `struct spi_driver_api` API but
is not implemented in the SPI emulator. This can cause a test calling
`spi_release()` to segfault. Add a stub implementation that just returns
zero.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
With commit 734adf52c6, the MCUX LPI2C config structure no longer
contains a direct base address pointer. The base address must be
accessed via DEVICE_MMIO_NAMED_GET. Some declarations in the LPCI2C
target mode handler still used the old method of accessing the base
address, causing a build failure. Fix these accesses to use the local
declaration of the "base" variable.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
clangsa reports the error
mdio_nxp_enet.c:245:10: error: label at end of compound statement:
expected statement
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Added Kconfig assignment of qspi timeout.
Per nrfx v3.2 addition of qspi timeout in config
struct.
Signed-off-by: Kelly Helmut Lord <kellyhlord@gmail.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The controller can implement a reception FIFO as deep as 256 bytes.
However, the computation made by the driver code to determine how many
bytes can be asked is stored in a signed 8-bit variable called rx_empty.
If the reception FIFO depth is greater or equal to 128 bytes and the FIFO
is currently empty, the rx_empty value will be 128 (or more), which
stands for a negative value as the variable is signed.
Thus, the later code checking if the FIFO is full will run while it should
not and exit from the i2c_dw_data_ask() function too early.
This hangs the controller in an infinite loop of interrupt storm because
the interrupt flags are never cleared.
Storing the rx_empty empty on a signed 32-bit variable instead of a 8-bit
one solves the issue and is compliant with the controller hardware
specifications of a maximum FIFO depth of 256 bytes.
It has been agreed with upstream maintainers to change the type of the
variables tx_empty, rx_empty, cnt, rx_buffer_depth and tx_buffer_depth to
plain int because it is most effectively handled by the CPUs. Using 8-bit
or 16-bit variables had no meaning here.
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
Add message buffer allowed values for S32K1xx devices. Except S32K14xW
parts which supports 64 MBs, the rest of the parts support a maximum of
32 MBs.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The entire switch statement is already wrapped in a lock which is
acquired just before configuring the gpio pin.
Signed-off-by: Yuval Peress <peress@google.com>
Alarm interrupt is disabled in cancel_alarm, we should re-enable it
in set_alarm, at meanwhile, should reset the compare register in
cancel_alarm to avoid the contention condition in
cancel_alarm & set_alarm in short time.
This change fixes the test case failure at
zephyr\tests\drivers\counter\counter_basic_api.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
The zephyr-gpio w1 driver introduced in this commit implements
all routines for the w1 api on top of the zephyr gpio driver.
W1 bit read, write, and reset operations are executed by
bit-banging the selected gpio.
Signed-off-by: Hudson C. Dalpra <hudson@bduncanltd.com>
Store the compile-time computed length of the `irq_count` into
a variable so that we have less to do in runtime.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Change the index variable type to `int` from `size_t` to compile
across 32bit and 64bit platforms without generating warnings.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Some STM32F4xx chips have an R division factor in PLL. Add possibility
to configure that.
Even though the output from the R division is not used, it can be
increased to reduce power consumption.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This change adds support for enabling ethernet MAC hardware checksum
offloading for STM32H7 based devices.
In Section 58.5.9 of the STM32H7 reference manual it mentions that
the STM32H7 ethernet MAC supports a Checksum Offload Module (COE).
I have tested the changes on my end where I enabled
CONFIG_ETH_STM32_HW_CHECKSUM and ensured that an application that
runs Zephyr on the STM32H7 can interoperate with a device with a
completely different implementation. Also, I deliberately made
the software not populate the IPv4 and UDP header checksum fields
in their respective headers and the COE was able to populate the
IPv4 and UDP header checksums.
Given that CONFIG_ETH_STM32_HW_CHECKSUM is not enabled by default
application developers have the option to either enable it or
disable it.
Signed-off-by: Chamira Perera <chamira.perera@audinate.com>
Reduce code-complexity of stm32_clock_control_init() function, which is
used and exists for both M4/M7 cores.
Replace dublicated code by proper preprocessor guarding.
This change shall reduce code-errors and copy-paste errors since same
functional code is present only once now.
Identify even more common code
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
Set suspended as initial power state, only when the
CONFIG_PM_DEVICE_RUNTIME config is enabled.
The initial state was incorrect, when CONFIG_PM_DEVICE=y and
CONFIG_PM_DEVICE_RUNTIME=n. In that case, the power state was SUSPENDED,
but the device was actually enabled.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Updated API version enables multi-instance GPIOTE driver.
Additionally obsolete symbol that was used to specify
API version in the past was removed.
Affected drivers have been adjusted and appropriate changes
in affected files have been made.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Like the stm32H5, stm32u5 usb device has an independent
power supply, but control bit is PWR_SVMCR_USV.
The control bit for the stm32H5 is PWR_USBSCR_USB33SV (no change)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
