In some ICs (including nRF54H20) the DEVICEID register is not part of
FICR, and thus it is not accessible to applications. Use instead the
device address, along with a couple of bytes from ER and IR, to
generated a unique device id.
At the same time update the pointer to the hal_nordic repo to pull in
https://github.com/zephyrproject-rtos/hal_nordic/pull/196.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
As there is no LiteUART it is more fitting
to rename the uart driver. This way it is also
more coherent with the other drivers and will
match the conditions in the MAINTAINERS.yml.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The enableRxRTS and enableTxCTS can only be configured when the
'UART_HAS_MODEM_SUPPORT' feature is enabled.
Uart has no 'error' IRQ on frdm_ke17z512, so update irq configuration
to configure the error interrupt when it exists.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
If it's a I3C v1.0 device without any HDR modes do not treat as an error
if GETCAPS gives no valid response.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Do not re-assign err from helper function, this just causes loss of
information from the helper function.
Only possible err returned is -EINVAL, so not a functional change.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
ESP32S3 requires ESP_ADC_CAL_VAL_EFUSE_TP_FIT calibration
scheme. The use of ESP_ADC_CAL_VAL_EFUSE_TP is not supported
in the SoC..
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Declare __stdout_hook_install in libc-hooks.h and use it in the console
drivers rather than redeclare it every time.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This is needed to avoid warnings about uninitialized
structure member, which was added in nrfx 3.6.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Update `ssd1306_write_default` to take into account the `segment_offset`
property. This is needed for some displays to show the image correctly.
Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
Necessary for supporting for EastRising 0.42 OLED display/board.
Some boards don't have external Iref set up. This is probably done in an
effort to save on component cost. This command is only documented in the
V1.1 revision of the SSD1306 datasheet.
See issue https://github.com/olikraus/u8g2/issues/1047
Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
The ICACHE must be disabled on STM32H5 series due to documented
behaviour of the flash controller, not to an errata.
For a more technical explaination: (see RM0492 for references)
- on STM32H5, the ICACHE block is interposed on C-bus between
the Cortex-M33 and the FLASH (§2.1.1)
- the ICACHE determines if accesses are cacheable or non-cacheable
based on an AHB attribute; the Cortex-M33 sets this attribute or
not depending on the MPU configuration (§8.4.6)
- when a cacheable access is requested by the Cortex-M33, if the
requested data is not present in ICACHE (cache miss), a cache line
refill (128-bit burst read) is performed (§8.4.7)
- however, all accesses to OTP and Read-Only regions of the FLASH must
be done with caching disabled (§7.3.2); indeed, the accesses MUST be
16 or 32-bit sized - otherwise, the flash interface raises a bus
error (§7.5.9 / Table 38 "OTP/RO access constraints").
This is the behaviour that was observed and lead to the introduction
of ICACHE disable code in 065a8f25e1.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit modifies the STM32 battery voltage sensor driver
to handle erroneous usage more gracefully. More precisely,
it now fails builds with an explicit error message when the
sensor is enabled but the corresponding ADC is not. This can
only happen on STM32 series with more than one ADC (e.g., H7).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit modifies the STM32 internal voltage reference sensor
driver to handle erroneous usage more gracefully. More precisely:
- driver no longer builds if no ADC node is enabled
- fail builds with an explicit error message when the sensor
is enabled but the corresponding ADC is not. This can only
happen on STM32 series with more than one ADC (e.g., H7).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit modifies the STM32 internal temperature sensor driver
to handle erroneous usage more gracefully. More precisely:
- driver no longer builds if no ADC node is enabled
- fail builds with an explicit error message when the sensor
is enabled but the corresponding ADC is not. This can only
happen on STM32 series with more than one ADC (e.g., H7).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
1. Support USB-C drivers TCPC, PPC, and VBUS with UTCPD H/W IP
2. UTCPD is interconnected with Timer-triggered EADC for updating
VBUS/VCONN voltage periodically
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When using the eeprom_target in 16-bit mode on rp2040, some issues in the
addressing have been observed where the read was executed before all writes
where finished.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Set the correct the phy_itface depending on the setting
Save few lines after resetting the priv->pcd structure
with the memset
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In lis2dux12_set_odr(), the call to stmemsc module lis2dux12_mode_set()
API is done with the .fs field left uninitialized, so setting the
underlying device regs in an unproper way.
Suggested-by: Luis Ubieda <luisf@croxel.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In the it8xxx2 chip, the interrupt for INT0 is reserved. However,in some
stress tests, the unhandled IRQ0 issue occurs. To prevent the system from
going directly into kernel panic, we implemented a workaround by
registering interrupt number 0 and doing nothing in the IRQ0 handler.
The side effect of this solution is that when IRQ0 is triggered, it will
take some time to execute the routine. There is no need to worry about
missing interrupts because each IRQ's ISR is write-clear, and if the
status is not cleared, it will continue to trigger.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
So far receving was possible in active mode, but IP and port information
was not fetched nor propagated to application layer. Support fetching that
information even in active mode, so that using bind() with recvfrom() is
working accordingly.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This is just a step forward to make cmd_ipd_parse_hdr() capable of parsing
IP address and port when CONFIG_WIFI_ESP_AT_PASSIVE_MODE=n. After obtaining
this information (IP and port) it will be simply much easier to write this
information into 'struct esp_socket' directly, instead of passing to upper
layer.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Treat ':' similar as ',', '\r' and '\n', so that AT response parameter
parsing can be gracefully stopped.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Use it to get information about RSSI. In subsequent commits this helper
will be used to get other information as well.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
'struct sockaddr_in' should contain port number in network byte order. This
means that htons() macro should be used, instead of ntohs().
This was working before since both htons() and ntohs() end up in calling
BSWAP_16().
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This variable is only used under DUAL_BANK condition and a warning
is generated in !DUAL_BANK case, so move its definition accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
During driver init make sure that the IRQ_CTL field is set before enabling
the interrupts. Fixes the i2c read error on startup.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
When QSPI configuration is the dual-flash, the total
flash size and erase size are doubled. This is handled
with a STM32_QSPI_DOUBLE_FLASH factor which doubles
the values of one qspi component.
Note that SFDP table is for ONE flash component.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
