This commit introduces a new interrupt controller driver used
for NXP's IRQ_STEER IP.
Apart from introducing the driver itself, this commit contains
the following changes:
1) Switch i.MX8MP to using the XTENSA core interrupt
controller instead of the dummy irqsteer one.
* this is required because the binding for the
irqsteer driver is no longer a dummy one
(since it's being used by the irqsteer driver).
As such, to avoid having problems, switch to
using another dummy binding.
2) Modify the irqsteer dummy binding such that it
serves the IRQ_STEER driver's needs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The command response buffer will return the total number of bytes
transfered. This will write back to the pointer which is to contain
the number of bytes sent or received.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This commit reworks the adltc2990_fetch_property_value function
to pass its result through a variable pointer instead of direct return.
This is done in part to separate the errno value being return in the
default case of the switch from the result of the function, but also
to make it easier the fix a Coverity issue regarding the unhandled
return values of i2c reads.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit adds a missing return value check. Since the I2C write
failed we release the semaphore and returning immediatly instead of
using goto exit.
Fixes#65352
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit adds a missing return value check for a register read.
The affected function was updated to use the regular errno return value
and to pass the result through a pointer instead.
Fixes#65346
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit adds a missing return value check during register read.
Added an imidiate return to remove the seemingly unwanted side
effect of also waiting for the bus read to work.
Fixes#65374
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit adds a missing return value check during register read.
Added an imidiate return to remove the seemingly unwanted side
effect of also waiting for the bus read to work.
Fixes#65383
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
Simplify the driver header implementation, so that there are not
structs and unions different per each situtaion, and make just one
function for the enet module drivers to call on each other. Also,
capitalize existing enums.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Make sure that events flagged as high priority are handled when
CONFIG_BT_RECV_BLOCKING is not defined.
Fix for #65892.
Signed-off-by: Michele Sardo <msmttchr@gmail.com>
Add an emulated DMA driver. Emulation drivers are great to have
for each driver API for multiple reasons:
- providing an ideal / model driver for reference
- potential for configurable backend support
- seamless integration with device tree
- multi-instance, etc, for all supported boards
- fast regression testing of app and library code
Since many other drivers and lbraries depend on DMA, this might
help us to increase test coverage.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
The LPS28DFW is an ultracompact, piezoresistive, absolute pressure sensor.
Compared to the LPS22DF, the LPS28DFW is waterproof and has a Dual FS
capability and does not have SPI. This commit extends the LPS22DF driver to
be compatible with the LPS28DFW device.
Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
Do not keep both DMA request enabled whenever the SSP is in use. Manage
the SSCR1_TSRE and SSCR1_RSRE bits in sync with the enabled directions.
When only playback is used there is no need to have the RX DMA request
enabled for example.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The receive FIFO needs to be drained in a different way depending when it
is done.
- before start
If the RX FIFO is in overflow state then we must read all the entries out
to empty it (it was after all full).
- before stop
The DMA might be already running to read out data. Check the FIFO level
change in one sample time which gives us the needed information to decide
to wait for another loop for the DMA burst to finish, wait for the DMA to
start it's burst (DMA request was asserted) or drain the FIFO directly.
No need to drain the RX fifo at probe time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
When loading the SSP configuration from a blob ignore the bits which would
enable the TX/RX or DMA requests at configuration phase.
The TX/RX enable and DMA request is handled by the driver itself. If the
blob wrongly enables any of the bits can have runtime (startup time)
seemingly random issues.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
For the Ambiq Apollo4x soc, every 32 pins share the same IRQ
number. irq_disable() should not be called for the pin interrupt
disablement, otherwise the interrupt of pins in the same GPIO
group will be disabled as well.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Use the "ambiq,gpio" binding to combine the "ambiq,gpio-bank"
child nodes for Apollo4 Plus soc.
Also update the GPIO driver accordingly.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Interupts should be enabled after int line configuration in bmi.
When the device goes to a suspended state interrupts must be disabled.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
The wake-up control input is IT8XXX2_IRQ_WU66.
Testing the wake-up functionality on GPF6 is normal.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The NET_L2_ETHERNET_MGMT configuration option is required to allow
setting MAC address or PLCA parameters with the LAN865x driver.
To avoid mistakes with per-board configuration files - it has been moved
to Kconfig and automatically selected when the driver support is enabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Handle the situation when OA TC6 compliant device signals to the host
that its configuration is lost - i.e. the SYNC bit in the footer is
cleared.
In this (unlikely happen) situation the device is reset and reconfigured.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
As part of IRQ service routine, there is at least one data transmission
performed between OA TC6 compliant device and HOST uC.
As this transmission can happen when there is no valid data to be read
(and its only purpose is to deassert the interrupt) the DV bit in footer
may be cleared. As this situation is expected with this approach - the
LOG level can be safely lowered from error to debug.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
According to the OPEN Alliance 10Base-T1x standard (point 7.7), it is
mandatory to read at least single data chunk (no matter if received data
is valid or not) to deassert the interrupt in the LAN865x (then the tc6
structure fields are also updated from the footer).
Current approach with reading OA_BUFSTS register was providing the
required information (RCA and TXC), but could cause transmission "stalls"
as this operation (i.e. control, not data transmission) is not causing
deassertion of the interrupt IRQ_N line from OA TC6 compliant device.
With this patch - the transmission is always performed at least once, so
interrupt is always deasserted.
As the functionality of oa_tc6_update_buf_info() - i.e reading value of
RCA and TXC - has been replaced with extracting data from footer, this
function can be safely removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In a previous change, STM32U5 GPDMA specific behavior was set into a
specific configuration applying only to few devices impacted by a specific
silicon erratum.
As part of this change, dma suspension before dma stop was set to apply
to the specific erratum workaround.
It appears, this was wrong and dma suspension before dma stop should
be done on all devices compatible with stm32u5 dma. This fix re-instantiate
the correct behavior.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Wakeup-source configuration is about configuring registers.
It belongs to uart_stm32_registers_configure().
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Some modems or networks require PAP authentication for successful
LCP handshake. Tested on U-blox SARA-R5 with zephyr,gsm-ppp.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
This renames the I2C 'DCR' mode to 'LVR' as that is the variable it
should be looking at and not the dcr value. This also fixes the get
'lvr' mode argument.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Either switching to CAN_DEVICE_DT_INST_DEFINE with [1] missed
updating mcp251xfd or missed in merge. Fix using function
pointer for init in mcp251xfd.
[1]: https://github.com/zephyrproject-rtos/zephyr/pull/62925
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Configure the sw trigger just after calibration
So the conversion can start on regular channel on the
software control bit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The Transfer Complete flag (TC) is used to check if a transfer is
complete. This mechanism is used before suspending the UART module to
make sure that all data are sent before the suspend procedure.
The UART ISR clears this flag after completion of a async transfer which
causes a hang during UART device suspend setup.
There is just no need to clear this flag in ISR, it is cleared every
time we start a new async transfer.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
In case of boards where REF_CLK signal is not connected
to the GPIO0 by default add the possibility to use
the optional GPIO16/GPIO17 as a REF CLK source.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Simplify and clarify spi_stm32_shift_m by splitting it in
3 smaller functions with clear names.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In H7, TXP indicates when its FIFO has room for, at least, one
packet. Thus, rename ll_func_tx_is_empty as ll_func_tx_is_not_full,
to be consistent in all platforms.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Avoind calling startMasterTransfer multiple times in a
transaction by moving it to the transceive() function.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
the FIFO Rx need to have a Minimum memory to works
distributed the rest of the ram_size memory between
the different TX FIFOs except the first which is
a control endtype with max data payload of 64 bytes
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
