The val2 calculation was done using (1000000 / 40960) as
multiplying factor, which was sometimes leading to a
int32 overflow. So, let's use the equivalent (but smaller)
(3125 / 128).
Fix#46615
Signed-off-by: Armando Visconti <armando.visconti@st.com>
If no " character is found in buffer by esp_pull_quoted() it
returns -EAGAIN which causes a loop that never ends. This is because
the buffer dont get filled up with new data so no " chrachter will be
found. This commit changes esp_pull_quoted() to only return -EAGAIN,
so the buffer can get filled with new data and thus the loop can come
to an end.
Signed-off-by: John Johnson <john.filip.johnson@gmail.com>
Pass DIEPTXF address instead of value to sys_read32() to prevent bus
fault when debug logging is enabled.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add a build-time assert for verifying that at least one of the supported
devicetree GPIO properties is present on each compatible devicetree node.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Introduce a XSPI driver to cover the common XSPI peripherals
of the stm32 mcu: X is for single or quad or octo or hexa
SPI bus access to external memories
DMA not supported in this version
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add driver, together with the corresponding dts binding and node in
the nRF54H20 SoC definiton, for the nRF temperature sensor that cannot
be accessed directly but only through nRF Services (nrfs) layer.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Force `\r\n` byte sequence for newline for the Xtensa simulator console
driver. This effectively mirrors the behavior of the UART console driver.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Be able to configure the clock frequency during runtime
using `i2c_configure()` and be able to use `i2c_get_config()`
of the i2c api for the esp32.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Fixes a bug where more than one thread trying to access
different PWM devices can cause erroneous behavior.
Co-authored-by: James Goppert <james.goppert@gmail.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Select that the STM32 driver has extended operations feature when
the FLASH_STM32_BLOCK_REGISTERS is set.
It allows using only block registers extended operation.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Some instances of the USDHC peripheral take longer to reset, and will
timeout with the previous delay of 100 cycles. Extend this delay to 1000
cycles to resolve this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove function for waiting for clock gate, as this is not used anywhere
within the USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some USDHC IP instances do not have the voltage control bit present, as
they can only operate at 3.3V. Move code to select 1.8V mode into a
separate helper, and guard the call to UDSHC_SelectVoltage() behind a
feature macro from MCUX SDK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CSI can connect to either a camera sensor (as on i.MX RT10xx) or
a MIPI CSI-2 receiver (as on i.MX RT11xx). To be generic, change the
naming from sensor to source.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Remove redundant `const` qualifiers in `struct modem_cellular_config` and
add `const` to the declaration to ensure the structure resides
in read-only memory (rodata).
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Instead of using floating point operations to compute the vref voltage,
it is possible to use the sensor_value_from_milli() function.
On a STM32G0, this saves 130 bytes of flash, excluding the FP library
needed on a FPU less MCU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Instead of using floating point operations to compute the vbat voltage,
it is possible to do the computation using 32-bit variables by
reordering operations and using the sensor_value_from_milli() function.
On a STM32G0, this saves 140 bytes of flash, excluding the FP library
needed on a FPU less MCU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit should add all the functionality needed for the DISPLAY
driver to work when PM is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add additional documentation and warnings around PXP usage. PXP rotation
is only intended to be used when framebuffers passed to the eLCDIF
display driver are equal in size to the screen.
Moreover, PXP rotation is flipped versus LVGL rotation. So a LVGL
rotation of 90 degrees requires the PXP to be set to rotate 270 degrees
to function as expected.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
FLEXSPI nor driver uses several LUTs for "scratch" commands during the
SFDP probe phase that are not needed once the flash is configured. Set a
second "end" marker we can use to configure the FLEXSPI MEMC driver, so
that we can indicate the true number of LUTs needed by this driver when
init is completed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Do not reset the FLEXSPI during init, as this will crash the chip if we
are running the MEMC driver in XIP mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for initializing the FLEXSPI when using a flash attached to
the FLEXSPI for XIP. This option is guarded behind a Kconfig, as
enabling it is dangerous and requires special care be taken by the user
to ensure that the configuration of pins and FLEXSPI settings will not
break support for reading the attached flash, as this will break XIP
support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use custom initialization priority for FLEXSPI MEMC driver. This may be
needed when the MEMC driver must initialize before a flash driver, and
before another MEMC driver (for an attached device, like PSRAM)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When multiple devices are used, the FLEXSPI will place their address
spaces sequentially (based on the chip select port used). Additionally,
each device must use different sections of the FLEXSPI LUT table.
Fix the following calculation issues with multi-device usage:
- correct calculation of LUT sequence indices for AHB commands
- correctly add address and sequence offset when submitting FLEXSPI IP
transfer
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update documentation for flash_config memc function, to correctly
reflect usage of the "lut_count" parameter
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Correct a trivial bug and doxygen documentation error
in which data_bits was missused instead of stop_bits.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Mateusz Grzywacz <amateusz.grzywacz@gmail.com>
For DA1469x if PM config is selected PM_DEVICE must also
be selected for GPIO to work when device enters/exists
deep sleep.
Previously GPIO and regulator drivers selected PM_DEVICE
when PM was enabled.
Now it is moved to SOC instead.
PM_DEVICE selection in GPIO could result in circular dependency
for mcux if MEMC_MCUX_FLEXSPI (which is already dependent on PM_DEVICE)
was to be additionally dependent on GPIO.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
- The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
- Disable the OTG_HS ULPI clock in sleep/low power mode,
- If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
usb_dc_stm32_init()),
[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
DWC USB 2.0 HS OTG Controller sets USB Reset interrupt after Reset
signalling starts, but before the High-Speed Detection Handshake. This
allows software to perform most of the reset handling even before the
connection speed is known. The device controller indicates High-Speed
Detection Handshake result is available in DSTS register by setting
Enumeration Done interrupt.
USB stack expects that the connection speed is known immediately after
UDC_EVT_RESET is submitted. Due to this expectation, it is important to
submit UDC_EVT_RESET only after Enumeration Done interrupt to prevent
the USB stack from reading (and storing) actual device speed before
it is known.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Makes the update channels function optional, this is only
implemented in one driver so can be safely omitted from most
drivers
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Checks that the supplied length is valid for the given driver
before passing it to the update function
Signed-off-by: Jamie McCrae <spam@helper3000.net>
The clk, dqs and ncs pins can be remapped between OSPI instances, but the
driver doesn't support it, yet. Therefore replace hard coded numbers to
device tree optional properties.
Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
Default priority set to Main Thread's and Stack-size set to 1KiB. This
should still allow for the System work-queue, considering this
Work-queue could be temporarily blocked on BT TX commands.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Stop relying on the system workqueue, as the BT TX APIs should
potentially block and now by design this will not work with the
Bluetooth Stack (for good reasons). Now the UART NUS driver has a
dedicated workqueue, which all NUS instances share.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Adapt the driver to verify if DMA buffers are located in noncacheable
memory when DCache is activated, in order to avoid cache coherency issues.
This is required until manual cache coherency management is implemented.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Two Kconfig symbols were tied to a board-specific DT nodelabel - namely
the `NRFX_UARTE_CONFIG_RX_CACHE_ENABLED` and `UART_<n>_RX_CACHE_SIZE`
were tied to `shared_ram3x_region` - but this is not necessary.
That DT node is where the UARTE driver RX/TX cache buffers are placed
in the default nRF54H20 DK memory map, but on another board, they could
be located somewhere else.
The exact memory sub-regions used for this purpose are indicated using
the `memory-regions` property on each UARTE instance, which should be
generic enough already, so let's use that instead.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This patch fixes a compiler warning about the val being used
uninitialized. The previously present if check did not seem to satisfy
compiler. Hence the val is now explictly initialized.
Signed-off-by: Balaji Srinivasan <balaji.srinivasan@nordicsemi.no>
Use "const LL_TIM_OC_GetCompareCHx" & "const LL_TIM_IsEnabledIT_CCx" with
STM32G4X series, following changes in stm32cube:stm32g4xx:drivers:
include:stm32g4xx_ll_tim.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Use "const LL_TIM_IC_GetCaptureCHx" & "const LL_TIM_IsActiveFlag_CCx"
with STM32G4X series, following changes in stm32cube:stm32g4xx:drivers:
include:stm32g4xx_ll_tim.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Use "const LL_DMA_IsActiveFlag_HTx", "const LL_DMA_IsActiveFlag_TEx",
"const LL_DMA_IsActiveFlag_TCx" and "const LL_DMA_IsActiveFlag_GIx" with
STM32G0X series, following changes in stm32cube:stm32g0xx:drivers:
include:stm32g0xx_ll_dma.h
Use "const LL_DMAMUX_IsActiveFlag_SOx","const LL_DMAMUX_IsActiveFlag_RGOx"
"const LL_DMAMUX_ClearFlag_SOx" and "const LL_DMAMUX_ClearFlag_RGOx" with
STM32G0X series, following changes in stm32cube:stm32g0xx:drivers:
include:stm32g0xx_ll_dmamux.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Use "const LL_TIM_OC_GetCompareCHx" & "const LL_TIM_IsEnabledIT_CCx" with
STM32F4X series, following changes in stm32cube:stm32f4xx:drivers:
include:stm32f4xx_ll_tim.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
