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drivers: usb: stm32: fix logic for USB clock configuration

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- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
  - The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
  - Disable the OTG_HS ULPI clock in sleep/low power mode,
  - If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
  OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
  usb_dc_stm32_init()),

[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY

Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This commit is contained in:
Armin Brauns 2024-03-28 13:03:30 +00:00 • committed by Alberto Escolar
commit 3ca157e76f
2 changed files with 33 additions and 36 deletions
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31
drivers/usb/device/usb_dc_stm32.c
View file

@ -265,27 +265,26 @@ static int usb_dc_stm32_clock_enable(void)
#endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
#if USB_OTG_HS_ULPI_PHY
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#else
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
#if !USB_OTG_HS_ULPI_PHY
/* Disable ULPI interface (for external high-speed PHY) clock in sleep
* mode.
*/
LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#endif
#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
#if !USB_OTG_HS_ULPI_PHY
/* Disable ULPI interface (for external high-speed PHY) clock in low
* power mode. It is disabled by default in run power mode, no need to
* disable it.
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) /* USB_OTG_HS_ULPI_PHY */
/* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode. It is
* disabled by default in run power mode, no need to disable it.
*/
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#else
LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
#endif
#if USB_OTG_HS_EMB_PHY
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#endif
#endif /* USB_OTG_HS_ULPI_PHY */
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */
return 0;
}

38
drivers/usb/udc/udc_stm32.c
View file

@ -974,33 +974,31 @@ static int priv_clock_enable(void)
#endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
#if USB_OTG_HS_ULPI_PHY
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#else
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
#if !USB_OTG_HS_ULPI_PHY
/* Disable ULPI interface (for external high-speed PHY) clock in sleep
* mode.
*/
LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) /* USB_OTG_HS_ULPI_PHY */
/* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode. It is
* disabled by default in run power mode, no need to disable it.
*/
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
#else
LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
#endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */
#if USB_OTG_HS_EMB_PHY
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
#endif
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
/* The USB2 controller only works in FS mode, but the ULPI clock needs
* to be disabled in sleep mode for it to work.
*/
LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
#endif
#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
#if !USB_OTG_HS_ULPI_PHY
/* Disable ULPI interface (for external high-speed PHY) clock in low
* power mode. It is disabled by default in run power mode, no need to
* disable it.
*/
LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
#endif /* USB_OTG_HS_ULPI_PHY */
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */
return 0;
}