drivers: usb: stm32: fix logic for USB clock configuration
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock - The constant has a slightly different name on stm32h7 - Otherwise, if the peripheral is OTG_HS: - Disable the OTG_HS ULPI clock in sleep/low power mode, - If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock. - Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in usb_dc_stm32_init()), [1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx [2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but without any way to actually connect a HS PHY Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
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2 changed files with 33 additions and 36 deletions
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@ -265,27 +265,26 @@ static int usb_dc_stm32_clock_enable(void)
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#endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
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#if USB_OTG_HS_ULPI_PHY
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#else
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
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#elif defined(CONFIG_SOC_SERIES_STM32H7X)
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#if !USB_OTG_HS_ULPI_PHY
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/* Disable ULPI interface (for external high-speed PHY) clock in sleep
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* mode.
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*/
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LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#endif
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#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
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#if !USB_OTG_HS_ULPI_PHY
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/* Disable ULPI interface (for external high-speed PHY) clock in low
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* power mode. It is disabled by default in run power mode, no need to
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* disable it.
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) /* USB_OTG_HS_ULPI_PHY */
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/* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode. It is
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* disabled by default in run power mode, no need to disable it.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#else
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LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
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#endif
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#if USB_OTG_HS_EMB_PHY
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
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#endif
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#endif /* USB_OTG_HS_ULPI_PHY */
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */
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return 0;
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}
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@ -974,33 +974,31 @@ static int priv_clock_enable(void)
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#endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
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#if USB_OTG_HS_ULPI_PHY
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#else
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
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#elif defined(CONFIG_SOC_SERIES_STM32H7X)
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#if !USB_OTG_HS_ULPI_PHY
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/* Disable ULPI interface (for external high-speed PHY) clock in sleep
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* mode.
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*/
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LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) /* USB_OTG_HS_ULPI_PHY */
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/* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode. It is
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* disabled by default in run power mode, no need to disable it.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
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#else
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LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
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#endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */
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#if USB_OTG_HS_EMB_PHY
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
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#endif
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
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/* The USB2 controller only works in FS mode, but the ULPI clock needs
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* to be disabled in sleep mode for it to work.
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*/
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LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
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#endif
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#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
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#if !USB_OTG_HS_ULPI_PHY
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/* Disable ULPI interface (for external high-speed PHY) clock in low
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* power mode. It is disabled by default in run power mode, no need to
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* disable it.
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*/
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LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
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#endif /* USB_OTG_HS_ULPI_PHY */
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) */
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) */
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return 0;
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}
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