Commit graph

1291 commits

Author SHA1 Message Date
Pisit Sawangvonganan
dcd0a2756d drivers: spi: remove '&' when assigning init_fn
Remove address-of operator ('&') when assigning `init_fn`
function pointer in `DEVICE_DT_INST_DEFINE` macro.

This change aims to maintain consistency among the drivers in
`drivers/spi`, ensuring that all function pointer assignments
follow the same pattern.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-08-08 06:08:04 -04:00
Fin Maaß
d71ad169d4 drivers: spi: litex: add litespi driver
add litespi driver for flash.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 12:39:02 +02:00
Fin Maaß
0f3955cc80 drivers: spi: litex: rework spi driver
rework the litex spi driver.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 12:39:02 +02:00
Fin Maaß
9a7037683d drivers: spi: litex: rename driver
rename litex spi driver.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 12:39:02 +02:00
Hao Luo
6ed058887e drivers: spi: simplified spi_ambiq_xfer function
Simplified spi transfer process to make it more readable

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-07-28 07:29:28 +03:00
Hao Luo
8379f64393 drivers: bluetooth: hci_ambiq: get the spi cfg from the device
Use the SPI configuration from the SPI device for data transaction.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-07-28 07:29:28 +03:00
Hao Luo
3faaaaba59 drivers: spi: Change to use software controlled cs in default
Added support for software controlled cs in Ambiq SPI drivers

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-07-28 07:29:28 +03:00
Liam Beguin
67544a6d2d spi: shell: add missing newline character
Add missing newline in help string.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
2024-07-12 09:12:47 -04:00
Alberto Escolar Piedras
0cf89bb8b4 drivers/spi/spi_xlnx_axi_quadspi: Build fix w CONFIG_SPI_ASYNC
Fix a build error when CONFIG_SPI_ASYNC is set.
The issue was detected by CI

```
spi_xlnx_axi_quadspi.c: In function 'xlnx_quadspi_isr':
spi_xlnx_axi_quadspi.c:489:21: error: 'ctx' undeclared
  489 |                 if (ctx->asynchronous) {
      |                     ^~~
```

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-07-10 19:13:46 -04:00
Nazar Palamar
bf17ba9d43 driver: spi: psoc6: fix build error in driver
fix build error related to pinctrl.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2024-07-08 15:51:21 +02:00
Chang Feng
971a0d1d93 driver: spi: gd32: fix spi reg clear wrong flag
SPI DMATEN and DMAREN flags are in SPI_CTL1 register. fixed wrong register.

Signed-off-by: Chang Feng <chang_196700@hotmail.com>
2024-07-01 09:16:22 +02:00
Adrien MARTIN
fd90c9ba21 drivers: spi: gecko: propagate spi config error
This commit catch the return code of the spi_config function and
early returns on error so that high level spi transfer api gets
the error too.

Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
2024-06-28 21:53:22 +02:00
Jordan Yates
91f8c1aea9 everywhere: replace #if IS_ENABLED() as per docs
Replace `#if IS_ENABLED()` with `#if defined()` as recommended by the
documentation of `IS_ENABLED`.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-06-28 07:20:32 -04:00
Fin Maaß
115d3d8aa7 drivers: spi: litex: add missing include
add missing include of `soc.h`.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-27 10:55:09 -04:00
Hao Luo
d1eea369b1 drivers: ambiq: Add dependencies to avoid showing to non-ambiq platforms
Fixed the Kconfig.ambiq under i2c and spi so that they don't litter.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-06-27 08:59:40 -04:00
Johan Carlsson
79a2e2445d drivers: spi: mcux_flexcomm: fix invalid dma config for last tx packets.
fixes an incorrect dma configuration. When lpc dma driver was extended
with gather/scatter support the spi dma driver stopped working.

Signed-off-by: Johan Carlsson <johan.carlsson@teenage.engineering>
2024-06-27 08:50:39 -04:00
Jordan Yates
07870934e3 everywhere: replace double words
Treewide search and replace on a range of double word combinations:
    * `the the`
    * `to to`
    * `if if`
    * `that that`
    * `on on`
    * `is is`
    * `from from`

Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-06-22 05:40:22 -04:00
Tomasz Bursztyka
b0e327bd9c drivers/spi: Fix context release in case of error
SPI context has to be released even in case of error.

Fixes: #72782

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@proton.me>
2024-06-22 05:39:55 -04:00
Ioannis Damigos
c7da55ef2c spi_smartbond: check that DMA controllers were provided
Check that DMA controllers were provided in
spi_smartbond_dma_deconfig()

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-18 14:36:38 -04:00
Ioannis Damigos
0a0bccabd8 drivers/smartbond: Fix PM device runtime support
Removed PM device runtime support from drivers in PD_SYS domain.

Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-18 14:36:38 -04:00
Robert Hancock
680fa154bf drivers: spi_xlnx_axi_quadspi: Reduce IRQ work
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2024-06-15 05:15:46 -04:00
Robert Hancock
68a24863c0 drivers: spi_xlnx_axi_quadspi: Optimize FIFO handling
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.

When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2024-06-15 05:15:46 -04:00
Robert Hancock
cff3811613 drivers: spi_xlnx_axi_quadspi: add STARTUP block workaround support
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.

See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2024-06-15 05:15:46 -04:00
Raffael Rostagno
7500f4e620 drivers: spi: Add suport to ESP32C6
Added GP-SPI2 (general purpose SPI2) support for ESP32C6

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Ioannis Karachalios
774ed60280 drivers: spi: smartbond: Add async API support
This commit should deal with adding support
for asynchronous operations. It also adds
support for DMA acceleration via a Kconfig
variable (enaled by default as DMA should
be considered scales faster than the
interrupt-driven approach).

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2024-06-13 20:17:04 -04:00
Tom Burdick
98b26c6ca8 rtio: Remove builtin iodev mpsc queue
I/O Devices were meant to be handles of sorts and had a built in mpsc queue
as this made sense initially. As time has gone on it turned out that often
we wanted the mpsc queue to be an implementation detail hidden in a driver.
In fact pretty much all drivers work this way now.

Keeping the struct mpsc queue as a member of rtio_iodev meant wasted memory
in cases where it wasn't used. It also meant a bit of confusion as the
queue might be accidently used in places where it shouldn't be.

Remove the mpsc queue member from struct rtio_iodev and the last remaining
usages of it. Will ensure RTIO for 3.7 LTS avoids causing unneeded churn
for future users.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2024-06-12 21:12:54 -04:00
Aksel Skauge Mellbye
d35eac2326 drivers: spi: gecko: Respect frequency configuration
This commit adds support for configuring SPI frequency per transaction.
The "clock-frequency" devicetree property is used as the default
frequency unless the peripheral being communicated with has a lower
"max-spi-frequency" (passed to the driver as spi_config::frequency).

An error is returned if the requested frequency is higher than the
hardware can support. This limit is half the peripheral clock (PCLK on
Series 2, HFPERCLK on Series 0/1) for SPI in controller mode.

Previously, the driver hard-coded 1 MHz operation. For backwards
compatibility, default to 1 MHz if the "clock-frequency" property is not
set in devicetree.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2024-06-12 18:52:17 +02:00
Aksel Skauge Mellbye
5513657e10 drivers: spi: gecko: Add support for devices with a single USART
This commit adds support for devices such as EFR32xG24 in the SPI
driver, as these devices only have a single USART peripheral.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2024-06-12 18:52:17 +02:00
Abderrahmane Jarmouni
533ade504d drivers: spi: stm32: minor fixes
Minor fixes & code improvements.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-06-12 14:28:35 +03:00
Lucas Tamborrino
604ea9243a drivers: spi: esp32: Fix clock initialization
The clock should be initialised only once at the
drivers init function.

Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-06-10 14:56:24 -05:00
Tom Burdick
d95caa51a4 sys: Add a lockfree mpsc and spsc queues
Moves the rtio_ prefixed lockfree queues to sys alongside existing
mpsc/spsc pbuf, ringbuf, and similar queue-like data structures.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2024-06-06 00:42:29 -07:00
Nikodem Kastelik
fc0718ed46 drivers: spi: nrf: add support for spim12x instances
SPIM12x instances can perform DMA only from memory region
that is cacheable by default.
SPIM12x instances pins are configured via CTRLSEL mechanism,
which prevents the GPIO registers from ensuring correct bus
state when peripheral does not drive the bus lines.
External configuration of SPIM12x ENABLE register fixes this issue.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-06-05 14:42:50 +01:00
Nikodem Kastelik
7080f0f83f drivers: spi: nrf: fix async cs deactivation
Chip Select signal must be deactivated only after transaction
is finalized. In async case this means it cannot be done from
`transceive` call context, as this context is left as soon as
transfer is initialized.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-06-05 14:42:50 +01:00
Nazar Palamar
7c3b66eac8 soc: psoc6: update pinctrl for PSoC6 MCU (legacy)
update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2024-06-04 16:35:39 +02:00
Tahsin Mutlugun
21723941a2 drivers: spi: Add MAX32690 SPI driver
Add SPI driver for Analog Devices MAX32690 MCU. Supports interrupt-based
transfers.

Co-Authored-By: Mert Vatansever <mert.vatansever@analog.com>
Co-Authored-By: Sadik Ozer <sadik.ozer@analog.com>
Co-Authored-By: Rob Cornall <rob.cornall@analog.com>
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2024-06-04 13:39:51 +02:00
Hao Luo
524ea22952 drivers: spi: Add support for Apollo3 SoCs SPI
This commit adds support for the SPI which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-06-04 13:39:27 +02:00
Jerzy Kasenberg
71ed2e4b02 drivers: spi: Add power management Smartbond SPI
Code adds pm action function that stores SPI configuration
before PD_COM is allowed to be turned off.

PM_DEVICE_RUNTIME scheme is also supported

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2024-05-29 12:03:29 +02:00
Yong Cong Sin
bbe5e1e6eb build: namespace the generated headers with zephyr/
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.

Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.

Updated the includes path of in-tree sources accordingly.

Most of the changes here are scripted, check the PR for more
info.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Joakim Andersson
3ad57e3030 drivers: spi_bitbang: Fix timing in SPI bitbang driver
Fix timing in SPI bitbang driver.
The issue occurs with CPHA=1 when the input data is changed immediately
after the clock shift on the last bit of the read.
Because we read the input bit after changing the clock, this bit
becomes invalid.
Instead of doing wait, clock-change, read. Do wait, read, clock-change.

Signed-off-by: Joakim Andersson <joerchan@gmail.com>
2024-05-27 05:42:26 -07:00
Aaron Ye
d84874309e drivers: spi: create Ambiq SPI BLEIF driver
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.

Signed-off-by: Aaron Ye <aye@ambiq.com>
2024-05-27 03:27:43 -07:00
Aurelien Jarno
18c73de93d drivers: spi: stm32: Skip pinctrl suspend/resume for subghzspi
Subghzspi instances cannot have any pinctrl configs. This causes a
failure of the power management suspend and resume operations for the
subghzspi instance because no "default" pinctrl is found.

Fix that by skipping the pinctrl parts on subghzspi instances.

At the same time fix a copy and paste in the suspend error message.

Fixes: b567a7db83

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2024-05-24 07:50:09 -04:00
Aurelien Jarno
858e8c51f1 drivers: spi: stm32: add runtime PM support
Add runtime power management suppor to the STM32 SPI driver. This allows
the driver to be suspended when not in use, and as a stop effect removes
the need to suspend/resume around each transition to stop mode.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2024-05-23 07:50:06 -04:00
Declan Snyder
eeb3e808f5 drivers: nxp: Add reset code to driver inits
Add peripheral reset handling code to driver init for:

- mcan
- i2c flexcomm
- spi flexcomm
- lpc mailbox
- mrt timer

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-21 16:49:42 -04:00
Rafał Kuźnia
8ec1e0cdaf drivers: spi_dw: add HSSI register layout
The Synopsys Designware SPI peripheral exists in two versions with
slightly different register layouts. Added a Kconfig option that makes the
driver compatible with the HSSI register layout.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-04-29 15:44:22 +02:00
Joakim Andersson
855c0d742b drivers: spi: Align SPI init priority with other devices
Align the SPI init priority with other devices.
Other bus-devices like UART and I2C are init at standard kernel
device level (50), but SPI is at 70 and there appears to not be
a reason for it.
GPIO is init at 40 so there should not be an issue to use the default.

Signed-off-by: Joakim Andersson <joerchan@gmail.com>
2024-04-25 18:00:20 -04:00
Nerijus Bendžiūnas
14338208ca spi: shell: fix copyright typo
Corrected copyright header.

Signed-off-by: Nerijus Bendžiūnas <nerijus.bendziunas@astrolightspace.com>
2024-04-25 07:24:14 -04:00
Abderrahmane Jarmouni
4af01814c4 drivers: spi: stm32: cache coherency management modifs
Expand cache coherency management code to all STM32 targets with DCACHE.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-04-19 16:40:33 +00:00
Steve Boylan
5b72665c47 drivers: spi: Add support for half-duplex (3-wire) SPI
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO.  To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.

The original PIO source code is also included as a reference.

Corrected 3-wire tx/rx counts.

Enable half-duplex code based on DTS configuration

Replace runtime checks with static BUILD_ASSERT()

Remove too-fussy Kconfig options

Removed PIO source per review request

Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
2024-04-18 08:09:15 -07:00
Nerijus Bendžiūnas
b394664dd9 spi: shell: add simple SPI shell
Inspired by I2C shell. Useful during
SPI device driver development or for debugging.

Usage example (read JEDEC ID):

```
uart:~$ spi conf spi4 1000000 oh
uart:~$ spi transceive 9f 00 00 00
TX:
00000000: 9f 00 00 00                                 |....             |
RX:
00000000: 00 ef 40 19                                 |....             |
```

Signed-off-by: Nerijus Bendžiūnas <nerijus.bendziunas@astrolightspace.com>
2024-04-18 08:08:02 -07:00
Dipak Shetty
c8e301ad78 drivers: spi: spi_mcux_lpspi.c: remove redundant assignments
Redundant kLPSPI_MasterPcsContinuous transfer config flag
is eliminated since this is set earlier.

Signed-off-by: Dipak Shetty <dipak.shetty@zeiss.com>
2024-04-18 08:06:42 -07:00