some platforms dont have these doze related symbols defined, and causes
a build error, fix with #ifdef bandaid.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Split the RX buffer into multiple sub-buffers aligned to DCACHE boundaries
to ensure proper operation during DMA transceive.
Signed-off-by: jacob kung <jacob.kung@egistec.com>
The Egis ET171 SPI controller was based on Andes ATCSPI200,
but has since been modified. In particular, the WrTranCnt and RdTranCnt
fields from the SPI Transfer Control Register have been moved to dedicated
Wr_Tran_Cnt and Rd_Tran_Cnt registers.
Signed-off-by: jacob kung <jacob.kung@egistec.com>
Remove the configs that are not actually used for anything anymore or
never were, or that are redundant with other configs, and don't have any
code changes outside of Kconfig to remove.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The dma driver was determining src_inc and dst_inc from the
config of the first block buffer and ignoring the config
flags for any additional buffers in the chain, which could
lead to incorrect transfers (e.g. in a multiple rx buffer
case, if the first buffer was to receive to NULL,
but the subsequent buffers were not NULL, the bug
would manifest as all transfers being made with
dst_inc of 0). Change the driver to setup
each dma descriptor according to the addr_adj flag
of each block_buffer.
Add check that peripheral transfers have addr_adj set to
NO_CHANGE instead of assuming it, to help catch errors.
Also now check for invalid addr_adj request of
decrement, which this controller doesn't support.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The spi_mcux_flexcomm driver uses a special last DMA blk_cfg
to trigger a release of the SPI chip select. This transfer
is always a 4-byte transfer, regardless of the width specified
during dma_configure().
The way the spi_mcux_flexcomm driver communicated this special
transfer was kind of a hack, where the dma_mcux_lpc driver would
assume that when a blk_cfg with source_addr_adj and dest_addr_adj
both set to NO_CHANGE was for this SPI_TX special case.
However, this is an unsafe hack since it is perfectly valid
to have dma use cases for both src/dest_addr_adj to be NO_CHANGE
that is not for SPI_TX. One example is when transmitting a
fixed/repeating value to a periperhal address (e.g. send 100
bytes of the same value from a single memory address over SPI).
This CL introduces a dma_mcux_lpc specific dma channel_direction
which the two drivers now use to cleary request this special
transfer case.
Signed-off-by: Mike J. Chen <mjchen@google.com>
In spi_mcux_transfer_next_packet(), if the next
transfer start fails, add calls to
spi_context_cs_control() to release cs and
spi_context_complete() with error code -EIO.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The current driver implementation would block even when the async
API was invoked, so it wasn't really async.
This CL also fully chains the DMA transfer using multiple dma blocks
and makes the number of dma blocks available a config value. The
increase in number of dma blocks is needed so that a spi_buf_set
that has many entries can be converted into chained dma transfers
with the last transfer in a separate block that will set the EOT flag.
Also make some improvements:
1) When doing single cnt transfer, don't use the SDK driver but
use a new fucntion spi_mcux_transfer_single_word().
It's much more efficient and does not use an ISR
like the SDK function does just to send one word.
2) Fix calls to spi_context_update_tx/rx() so that the
correct word size is passed in, instead of previously
being hardcoded to 1. This only matters when word size
is two. Evaluate the word_size_bytes and word_size_bits
once and store the values in data instead of computing
it multiple times in various parts of the driver
3) When CONFIG_SPI_MCUX_FLEXCOMM_DMA is defined, we
do not use the IRQ handler, so add #ifdefs to compile
that code out. This reduces code size.
Signed-off-by: Mike J. Chen <mjchen@google.com>
This reverts commit a3530d6a43.
This change incorrect if chip-select is via a GPIO pin,
released by spi_context_cs_control(), and not the controller
default chip-select pin that can be released using a final
FIFOWR.
When GPIO is used for chip-select control, the chip-select could
be released too soon because the transfer callback is invoked
when the last byte is put into the TX FIFO but that byte might
not yet have clocked out yet on the SPI pins. The rx part of
the transfer is really what completes the transfer so ignoring
it is incorrect.
We could try to special case and use ignore only when
spi_context_cs_control() does nothing, but since it is a very
small optimization, it doesn't seem worth the extra
complexity.
Signed-off-by: Mike J. Chen <mjchen@google.com>
support interrupts for rx_ready, so we can use the
time we are waiting for other stuff.
implement async spi transfers.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
To reduce power consumption, the SPI clock is gated when no spi
transaction is in progress. With this mechanism, current
consumption is reduced by approximately 0.1mA when cpu idle.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit removes gpio-based cs support as it8xxx2 spi
only supports transactions using the dedicated cs pin.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The p_context no longer has the const type, so all
Renesas-supported drivers need to be updated accordingly.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Some nRF SoCs (i.e. nRF54H20) can peform DMA transfers
only from specific memory regions - `dmm` facilitates that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The CPOL and CPHA mode handling logic in the SPI configuration was
corrected to ensure proper evaluation of the SPI mode bits.
Evaluate CPOL and CPHA bits using value of cpol_mode and cpha_mode:
`(SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) != 0` and
`(SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) != 0`.
This fix ensures that the SPI configuration is robust and adheres to
expected behavior when setting CPOL and CPHA modes.
Signed-off-by: Xiaolu Sun <xiaolu.sun@intel.com>
XIP may indicate that the program is executed either in local memory
or flash. However, the SPI node is only used as a flash controller
when the program is executed in flash.
Therefore, optimize the related checks to ensure that when XIP is
enabled but the program is executed in local memory, the SPI node
can still be used.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Due to the hardware limitations of the ATCSPI200 IP, the transmission
and reception counts must be consistent. If there is a mismatch in
length, dummy data needs to be transmitted or received.
Under this limitation, using the spi_context_xx related APIs to
determine whether the transmission is complete may cause issues in
certain situations.
Therefore, additional variables are set to record the exact number of
bytes need to be transmitted or received.
2. Also, fix some inaccuracies in configuring DMA transfers.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
SPI(M/S)20 and SPIM(M/S)21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
If `desired_delay_ns` is `0`, it is much saner to set the delay to `0x00`
than to underflow and set it to `0xff`, which is the current behavior.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
Perform DMA operations using GDMA driver instead of relying on
HAL functions. Prevents eventual conflicts between SPI and GDMA
drivers when other peripherals also use DMA.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Don't automatically enable device runtime PM on the SPI port just
because `PM_DEVICE_RUNTIME` is enabled. Require the user to explicitly
call `pm_device_runtime_enable` on the port, or add
`zephyr,pm-device-runtime-auto` to the devicetree node.
Through the usage of `pm_device_driver_init`, the default clock control
and pinctrl handling can all be contained in `spi_stm32_pm_action`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Configure the initial pin state of the SPIM peripheral to SLEEP, not
DEFAULT. This fixes the pins being configured in DEFAULT until the first
time the interface is used if `zephyr,pm-device-runtime-auto` is
enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
spi_configure was returning HAL error codes that are incompatible with
Zephyr error definitions straight back to the caller. Replace these with
error codes that Zephyr can correctly interpret.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Driver was not handling SPI word sizes other than 8 bits. Apply DFS
shift wherever necessary to support non 8-bit transfers.
DMA mode cannot support word sizes that are less than 8 bits so return
-ENOTSUP if word size less than 8-bits is required.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
This patch adds the initial support for the OMAP Multi-Channel SPI. Some
things should be noted however:
- DMA xfers are not supported yet. Only PIO is supported as of now.
- Multi-Channel controller is not supported yet. Only single-channel
controller mode is supported, this means that the controller can xfer
messages with one slave at a time.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Fix regression caused by memset() replacement to zero volatile struct.
ESP32-C6 data_buf struct differs from other SoCs and needs custom
handling.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This is not really high priority to support and is disrupting test
reporting, for now just hotfix the test by returning that this is not
supported, it's not really necessary anyways, there's multiple ways to
call the API to achieve the same effect.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This data update returns an error, we should propogate it where it is
called if there is an error returned.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Function spi_context_release reads the content of ctx->config without
checking first if it is set. In many drivers (including STM32), when a bad
configuration is made for the first transaction, ctx->config is not set,
and spi_context_release is called, resulting in hard fault.
This commit adds a check that ctx->config exists before reading it to
avoid this problem.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace memset() with an explicit loop to zero the data_buf array,
which is part of a volatile struct. Standard memset does not guarantee
volatile stores, which can lead to incorrect hardware access.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The clock get rate api can be slow in certain targets and thus slowing
each SPI transaction. Instead on startup fetch the clock rate and store
this in ram. Then each spi configure action is simply reading that
variable
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The interrupt handling was not deterministic before because it relied
on "guessing" if the lpspi was a v1 type that was stalling due to design
errata. This obviously ended up being wrong in some cases. So we really
need to fix this so that it is deterministic, and my idea to do that is
to explicitly count how many words we have written to the TX fifo
throughout the whole transfer.
As a side effect of making the IRQ more deterministic, we can't support
the SPI_HOLD_ON_CS flag for v1 LPSPI anymore. It is fundamentally
impossible due to the fact that the transfer can only complete in
hardware as a result of CS deasserting. If this is absolutely a
requirement to support this flag in the future, my recommendation is to
update the driver so that it muxes the pin to a gpio before ending the
transfer, but that would kind of defeat the point of having a native CS,
at least at the end of the xfer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add overlay file for RT1170 EVK and simply existing flexio spi overlay
file for RT1060 EVKC and RT1064 EVK. One flexio-spi interface for both slow
and fast tests. Fast baud rate set to 16Mbps now.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max baud rate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and RX, if timer comparison value is not accurate, RX error happens on
high baud rate. This is the reason why test fails on RT1060.
also fix a error on FlexIO clock ID calculation.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
STM32H7 spi_loopback test fails since the introduction of a test enabling
SPI_HOLD_ON_CS.
This uncovered an issue where the SPI ISR is constantly called if the SPI
is not disabled, even if the interrupt enable register is completely
cleared.
A workaround is to disable the SPI IRQ at the NVIC level when
SPI_HOLD_ON_CS is used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
