drivers: spi_mcux_lpspi: Clean up configure func
Do all input validation etc BEFORE setting up configuration, instead of mixing these things everywhere. Also condense the formatting of the code. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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b7c35fb569
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1 changed files with 22 additions and 31 deletions
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@ -160,49 +160,25 @@ static int spi_mcux_configure(const struct device *dev, const struct spi_config
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const struct spi_mcux_config *config = dev->config;
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struct spi_mcux_data *data = dev->data;
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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lpspi_master_config_t master_config;
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uint32_t clock_freq;
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uint32_t word_size;
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if (spi_cfg->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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LPSPI_MasterGetDefaultConfig(&master_config);
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if (spi_cfg->slave > CHIP_SELECT_COUNT) {
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LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, CHIP_SELECT_COUNT);
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return -EINVAL;
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}
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (word_size > MAX_DATA_WIDTH) {
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LOG_ERR("Word size %d is greater than %d", word_size, MAX_DATA_WIDTH);
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return -EINVAL;
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}
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master_config.bitsPerFrame = word_size;
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master_config.cpol = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
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? kLPSPI_ClockPolarityActiveLow
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: kLPSPI_ClockPolarityActiveHigh;
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master_config.cpha = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
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? kLPSPI_ClockPhaseSecondEdge
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: kLPSPI_ClockPhaseFirstEdge;
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master_config.direction =
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(spi_cfg->operation & SPI_TRANSFER_LSB) ? kLPSPI_LsbFirst : kLPSPI_MsbFirst;
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master_config.baudRate = spi_cfg->frequency;
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master_config.pcsToSckDelayInNanoSec = config->pcs_sck_delay;
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master_config.lastSckToPcsDelayInNanoSec = config->sck_pcs_delay;
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master_config.betweenTransferDelayInNanoSec = config->transfer_delay;
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master_config.pinCfg = config->data_pin_config;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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@ -226,18 +202,33 @@ static int spi_mcux_configure(const struct device *dev, const struct spi_config
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}
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}
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LPSPI_MasterInit(base, &master_config, clock_freq);
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if (IS_ENABLED(CONFIG_DEBUG)) {
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base->CR |= LPSPI_CR_DBGEN_MASK;
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}
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LPSPI_MasterTransferCreateHandle(base, &data->handle, spi_mcux_master_callback, data);
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LPSPI_SetDummyData(base, 0);
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data->ctx.config = spi_cfg;
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LPSPI_MasterGetDefaultConfig(&master_config);
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master_config.bitsPerFrame = word_size;
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master_config.cpol = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
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? kLPSPI_ClockPolarityActiveLow
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: kLPSPI_ClockPolarityActiveHigh;
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master_config.cpha = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
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? kLPSPI_ClockPhaseSecondEdge
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: kLPSPI_ClockPhaseFirstEdge;
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master_config.direction =
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(spi_cfg->operation & SPI_TRANSFER_LSB) ? kLPSPI_LsbFirst : kLPSPI_MsbFirst;
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master_config.baudRate = spi_cfg->frequency;
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master_config.pcsToSckDelayInNanoSec = config->pcs_sck_delay;
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master_config.lastSckToPcsDelayInNanoSec = config->sck_pcs_delay;
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master_config.betweenTransferDelayInNanoSec = config->transfer_delay;
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master_config.pinCfg = config->data_pin_config;
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LPSPI_MasterInit(base, &master_config, clock_freq);
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LPSPI_MasterTransferCreateHandle(base, &data->handle, spi_mcux_master_callback, data);
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LPSPI_SetDummyData(base, 0);
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return 0;
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}
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