Commit graph

1291 commits

Author SHA1 Message Date
Andreas Sandberg
d33b89befe drivers: spi: spi-bitbang: Add support for half duplex
Implement support for half duplex communication in the bit bang SPI
driver. The SPI driver will use the MOSI pin is for both TX and RX
operations when using half duplex mode.

In half-duplex mode, the driver configures the MOSI pin as an input
pin for input only transactions. Transactions that are bidirectional
are forbidden. After an SPI transaction, the MOSI pin is left as an
input if it was an RX transaction or an output after a TX
transaction. Like before, the MOSI pin is initialized as an
(inactive) output pin when the bus is initialized.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-13 10:15:00 +02:00
Gerard Marull-Paretas
c2d699ec2d drivers: spi: sifive: remove CONFIG_SIFIVE_SPI_0_ROM
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-11 17:56:55 +02:00
Piotr Dymacz
20cb405e17 drivers: adjust cc13xx_cc26xx drivers for hal_ti update
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.

This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2022-07-08 09:37:43 +02:00
Anas Nashif
49b36ead95 drivers: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 11:00:45 -04:00
Andreas Sandberg
a05e8dcc5e drivers: spi: spi-bitbang: Fix CS glitch in transceive
spi_context_cs_configure_all() is currently called from
spi_bitbang_transceive(). This causes a glitch when combined with
SPI_HOLD_ON_CS is used.

Move the initialization to spi_bitbang_init which is what the other
SPI drivers seem to do.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-06 11:11:14 +02:00
Andreas Sandberg
65252ffd95 drivers: spi: spi-bitbang: Initialize CS GPIOs
The SPI bitbang driver doesn't correctly initialize the list of CS
GPIOs. As a consequence, SPI buses using the bitbang driver won't
drive CS low. Add the missing initialization.

Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
2022-07-06 11:11:14 +02:00
Erwan Gouriou
890d42759b drivers: spi: stm32: Use 'st,stm32h7-spi' compatible input when possible
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-07-04 14:23:34 +00:00
Jose Alberto Meza
b4d82289e1 drivers: spi: xec: mec172x: Reflect update device tree properties
Propagate update device tree properties.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-07-04 16:18:42 +02:00
Gerard Marull-Paretas
4946a15f15 soc: arm: gigadevice: use common API headers
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.

This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-06-22 18:41:19 +09:00
Anas Nashif
2d87948818 drivers: ipm/spi/intc: remove Intel S1000 support
Remove intel_s1000_crb support. The board is no longer available or
supported in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-13 16:19:51 -04:00
Naga Sureshkumar Relli
248047323e drivers: spi: Add support for Polarfire SOC QSPI
This patch adds driver for the Microchip Polarfire SOC MSS QSPI
controller.
The interrupts of the MSS QSPI are routed through PLIC(Platform level
interrupt controller).

Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
2022-06-13 12:11:28 +02:00
Marcin Niestroj
774a3cd756 drivers: spi: spi_nrfx_spim: fix !LEGACY_INCLUDE_PATH
Add missing zephyr/ prefix to fix CONFIG_LEGACY_INCLUDE_PATH=n build.

Fixes: d64dc771f3 ("drivers: spi: spi_nrfx_spim: utilize EasyDMA property
  from devicetree")

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-06-06 12:07:22 +02:00
Adam Wojasinski
d64dc771f3 drivers: spi: spi_nrfx_spim: utilize EasyDMA property from devicetree
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.

When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2022-06-05 14:27:29 +02:00
Shawn Nematbakhsh
3386b853ac drivers: spi_sifive: Optimize xfer to minimize downtime between frames.
The SPI peripheral on SiFive parts uses FIFOs for Rx and Tx (FIFO size
undocumented, but empirically found to be 8 bytes on FE310, likely
identical on FU540 / FU740). Make use of these FIFOs in order to
continuiously feed Tx data as available.

Verified to transmit 1 MHz SPI @ 200 MHz coreclk / tlclk on FE310
continuously without downtime between frames.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-06-05 14:14:59 +02:00
Shawn Nematbakhsh
e17d5ed282 drivers: spi_sifive: Use uint8_t data/buffer types to match spi_context.
spi_context uses uint8_t buffers, and HW rxdata / txdata registers only
contain 8 bits of data (along with b31 full / empty flag), so uint8_t is
appropriate.

Suggested-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-06-05 14:14:59 +02:00
Michal Sieron
9f6c531da0 drivers: spi: spi_litespi: Update driver registers
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-05-27 15:27:11 -07:00
Nazar Palamar
d940d23c10 modules: hal_infineon: added initial Kconfig and CMakeLists.txt
- added initial Kconfig
- added initial CMakeLists.txt (root, core-lib,  mtb-pal-cat1)
- updated module, driver and soc to use CONFIG_USE_INFINEON_xx
  defines from modules/hal_infineon/Kconfig

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2022-05-13 21:34:59 +02:00
Jordan Yates
c28874657b spi: spi_b91: use new DT_INST_STRING_TOKEN macro
Use the dedicated `DT_INST_STRING_TOKEN` macro instead of manually
retrieving `DT_DRV_INST`.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-05-13 14:17:08 +02:00
Erwan Gouriou
0b65c1c619 drivers/spi: stm32: Use alt clock freq if available
Add support for an alternate clock. If available,
alternate clock is enabled and used to get the
device clock rate.

Fixes #41650

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Gerard Marull-Paretas
fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Henrik Brix Andersen
c83a0d5d1f drivers: spi: rv32m1: lpspi: add pinctrl support
Add pinctrl support to the OpenISA RV32M1 LPSPI SPI driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Carlo Caione
69b28bfd07 pm: policy: Consider substates for state lock functions
Extend the current pm_policy_state_lock_*() functions to support
substates.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-04-28 16:32:23 +02:00
Glauber Maroto Ferreira
9354749cb5 esp32c3: drivers: spi: removal of unused definitions
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.

Refactor device tree macros usage to make usage of
SPI instances more general.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira
6303118260 esp32s2: drivers: spi: removal of unused definitions
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira
40a80d236e drivers: spi: esp32: use pinctrl API
and removes references/usage of old pinmux properties.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Vaishnav Achath
ace77c71e9 drivers: CC1XX/CC26XX based boards: transition to pinctrl driver
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.

Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
2022-04-18 18:19:46 -04:00
Attie Grande
cfad60d4dd spi: sam0: fix fast-rx path, and refresh comments
The SAM0 fast-path implementation was broken, and partially fixed in
commits 8181eed and 8a99bd0...

This patch resolves an issue where the MSB is always zero on SAML21
parts, and appears to follow suit with the previous patches.

This patch also refreshes the commentary, and removes mention of the
"interleaved" operation that is no longer used - which appears to have
been problematic in the past.

In addition to this, it also resolves an off-by-one error in both the
fast_rx and fast_rxrx paths, which would have been tripped when
transmitting a zero-byte buffer.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-04-13 13:32:45 -07:00
Daniel DeGrasse
c637d7d672 drivers: spi: spi_mcux_flexcomm: add pinctrl support to lpc spi driver
add pinctrl support for spi_mcux_flexcomm driver.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-06 20:57:22 -07:00
Shawn Nematbakhsh
c74526919d soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.

This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Andrzej Głąbek
586e26e8fc soc: nrf: Use data from DTS to populate HAS_HW_NRF_* Kconfig options
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-04-02 15:14:38 +02:00
Sylvio Alves
e04172fcef drivers: spi: esp32c3: add master init call
ESP32C3 requires master init call to enable its clock
gate. Without this, SPI interface may not initialize
properly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-04-01 13:00:16 -05:00
Bartosz Bilas
1d40d4fa5a drivers: spi_handlers: switch to gpio_dt_spec member
Don't use the old gpio_dev spi_cs_control's member
since it's been deprecated in favor of gpio_dt_spec.

Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
2022-03-29 10:24:56 -05:00
HaiLong Yang
9d2425c186 drivers: spi: introduce gd32 spi driver
Add a simple gd32 spi driver.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-03-29 10:21:15 -05:00
Gerson Fernando Budke
fbddf7847d drivers: spi: Add sam0 support to pinctrl
This add support to pinctrl at Atmel sam0 spi driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Gerson Fernando Budke
38d0659931 drivers: spi: Update sam driver to use pinctrl
This update Atmel sam spi driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-03-24 15:45:37 -07:00
Filip Kokosinski
38f38e0be8 boards: FE310-based boards: transition to pinctrl driver
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Daniel DeGrasse
6545a3d0fa drivers: spi: enable pinctrl for spi_mcux_lpspi
Enable pinctrl for lpspi driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Daniel DeGrasse
f400aa41cd boards: remove spi pinmux setting for kinetis boards
Remove spi pinmux setting for kinetis boards with dspi, as dspi driver
supports pinctrl

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Daniel DeGrasse
f90c356025 drivers: spi: enable pinctrl for kinetis dspi driver
Enable pinctrl unconditionally for kinetis dspi driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-22 12:36:04 +01:00
Andrzej Głąbek
a5234f3647 soc_nrf_common: Extend and rename the NRF_DT_ENSURE_PINS_ASSIGNED macro
Extend the macro with checks for DT properties related to pin
assignments that are defined but would be ignored, depending on
whether PINCTRL is enabled or not, what presumably indicates
a resulting configuration different from what the user expects.

Add also a possibility to indicate that the pinctrl-1 property
should not be checked because the caller does not support the
sleep state.

Rename the macro so that its name better reflects its function.
Update accordingly all drivers that use it.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-18 16:26:21 +01:00
Gerard Marull-Paretas
b618bdbaad drivers: spi: cc13xx_cc26xx: remove CONFIG_PM guards
API provides no-op fallback when CONFIG_PM=n

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-16 15:26:47 +01:00
Gerard Marull-Paretas
5a71eeb35c pm: policy: move constraints to policy API
The pm_constraint_* APIs were effectively used by the policy manager
only. This patch renames the API to the policy namespace and makes its
naming more explicit:

- pm_constraint_set -> pm_policy_state_lock_get()
- pm_constraint_release -> pm_policy_state_lock_put()
- pm_constraint_get -> pm_policy_state_lock_is_active()

The reason for these changes is that constraints can be of many types:
allow/disallow states, impose latency requirements, etc. The new naming
also makes explicit that the API calls will influence the PM policy
behavior.

All drivers and documentation have been updated accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-16 15:26:47 +01:00
Tomasz Bursztyka
16062c2e5a drivers: constify all device instances
Run cocci script to constify device instances.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2022-03-16 12:33:12 +01:00
Nazar Kazakov
9713f0d47c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-14 20:22:24 -04:00
Francois Ramu
61bef2087f drivers: spi: stm32 spi with dma must enable cs after periph
When using DMA to transfer over the spi, the spi_stm32_cs_control
is done after enabling the SPI. The same sequence applies
in the transceive_dma function as in transceive function

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-03-11 10:59:05 +01:00
Gerard Marull-Paretas
95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Andrzej Głąbek
32b9e65e4b drivers: spi: nrfx: Add support for pinctrl
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-09 12:05:22 +01:00
Andrzej Głąbek
2a87e04ce6 drivers: spi: nrfx: Clean up code
- clean up registration of the drivers with the logging subsystem
- use consistent naming of local variables accessing configuration
  and runtime data of driver instances, for easier code maintenance

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-03-09 12:05:22 +01:00
Jay Vasanth
535c20e490 qmspi: MEC172x: fix unused variable warning
Fix unused variable warning when CONFIG_SPI_ASYNC
is not defined

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00
Jay Vasanth
99c89ebb78 qmspi: update MEC172x qmspi module for pinctrl
Changes to qmspi module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-03-07 11:03:06 +01:00