Fixes division by zero exception when SPI is configured to operate in mode3
whit CS controlled by software.
Such exception occurred because data->dfs is listed as the denominator in
a division inside the spi_esp32_transfer() function which is called from
spi_esp32_configure() (before assigning a value to data->dfs) inside
transceive() in the condition where mode 3 is chosen as the SPI operating
mode and the chip select is configured to be software-controlled.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Add checks to return value of esp_intr_alloc to avoid drivers init
returning 0 when interrupt allocation fails.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Update spi_bitbang_transceive_async function parameter to it match
with correct one that declared in struct
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Transmit/write buffers are expected to be constant values given to the
operation to transmit but not mutate. Seperate the OP_TX and OP_RX
operation description unions.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Remove address-of operator ('&') when assigning `init_fn`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/spi`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fix a build error when CONFIG_SPI_ASYNC is set.
The issue was detected by CI
```
spi_xlnx_axi_quadspi.c: In function 'xlnx_quadspi_isr':
spi_xlnx_axi_quadspi.c:489:21: error: 'ctx' undeclared
489 | if (ctx->asynchronous) {
| ^~~
```
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit catch the return code of the spi_config function and
early returns on error so that high level spi transfer api gets
the error too.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
fixes an incorrect dma configuration. When lpc dma driver was extended
with gather/scatter support the spi dma driver stopped working.
Signed-off-by: Johan Carlsson <johan.carlsson@teenage.engineering>
Removed PM device runtime support from drivers in PD_SYS domain.
Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This commit should deal with adding support
for asynchronous operations. It also adds
support for DMA acceleration via a Kconfig
variable (enaled by default as DMA should
be considered scales faster than the
interrupt-driven approach).
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
I/O Devices were meant to be handles of sorts and had a built in mpsc queue
as this made sense initially. As time has gone on it turned out that often
we wanted the mpsc queue to be an implementation detail hidden in a driver.
In fact pretty much all drivers work this way now.
Keeping the struct mpsc queue as a member of rtio_iodev meant wasted memory
in cases where it wasn't used. It also meant a bit of confusion as the
queue might be accidently used in places where it shouldn't be.
Remove the mpsc queue member from struct rtio_iodev and the last remaining
usages of it. Will ensure RTIO for 3.7 LTS avoids causing unneeded churn
for future users.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This commit adds support for configuring SPI frequency per transaction.
The "clock-frequency" devicetree property is used as the default
frequency unless the peripheral being communicated with has a lower
"max-spi-frequency" (passed to the driver as spi_config::frequency).
An error is returned if the requested frequency is higher than the
hardware can support. This limit is half the peripheral clock (PCLK on
Series 2, HFPERCLK on Series 0/1) for SPI in controller mode.
Previously, the driver hard-coded 1 MHz operation. For backwards
compatibility, default to 1 MHz if the "clock-frequency" property is not
set in devicetree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for devices such as EFR32xG24 in the SPI
driver, as these devices only have a single USART peripheral.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The clock should be initialised only once at the
drivers init function.
Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Moves the rtio_ prefixed lockfree queues to sys alongside existing
mpsc/spsc pbuf, ringbuf, and similar queue-like data structures.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPIM12x instances can perform DMA only from memory region
that is cacheable by default.
SPIM12x instances pins are configured via CTRLSEL mechanism,
which prevents the GPIO registers from ensuring correct bus
state when peripheral does not drive the bus lines.
External configuration of SPIM12x ENABLE register fixes this issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Chip Select signal must be deactivated only after transaction
is finalized. In async case this means it cannot be done from
`transceive` call context, as this context is left as soon as
transfer is initialized.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This commit adds support for the SPI which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Code adds pm action function that stores SPI configuration
before PD_COM is allowed to be turned off.
PM_DEVICE_RUNTIME scheme is also supported
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
