drivers: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single line statements shall have braces. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
a408b56e12
commit
49b36ead95
45 changed files with 243 additions and 146 deletions
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@ -761,8 +761,9 @@ static int adc_npcx_init(const struct device *dev)
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/* Configure the ADC clock */
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prescaler = ceiling_fraction(data->input_clk, NPCX_ADC_CLK);
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if (prescaler > 0x40)
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if (prescaler > 0x40) {
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prescaler = 0x40;
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}
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/* Set Core Clock Division Factor in order to obtain the ADC clock */
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SET_FIELD(inst->ATCTL, NPCX_ATCTL_SCLKDIV_FIELD, prescaler - 1);
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24
drivers/cache/cache_aspeed.c
vendored
24
drivers/cache/cache_aspeed.c
vendored
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@ -139,8 +139,9 @@ int cache_data_all(int op)
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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/* enter critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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ctrl &= ~DCACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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@ -151,8 +152,9 @@ int cache_data_all(int op)
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__DSB();
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/* exit critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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@ -171,8 +173,9 @@ int cache_data_range(void *addr, size_t size, int op)
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}
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/* enter critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
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@ -184,8 +187,9 @@ int cache_data_range(void *addr, size_t size, int op)
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__DSB();
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/* exit critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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@ -201,8 +205,9 @@ int cache_instr_all(int op)
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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/* enter critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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ctrl &= ~ICACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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@ -212,8 +217,9 @@ int cache_instr_all(int op)
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__ISB();
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/* exit critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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@ -234,8 +240,9 @@ int cache_instr_range(void *addr, size_t size, int op)
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n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
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/* enter critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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for (i = 0; i < n; i++) {
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syscon_write_reg(dev, CACHE_INVALID_REG, 0);
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@ -245,8 +252,9 @@ int cache_instr_range(void *addr, size_t size, int op)
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__DSB();
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/* exit critical section */
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if (!k_is_in_isr())
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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@ -36,8 +36,9 @@ static inline int npcx_clock_control_on(const struct device *dev,
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struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
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const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT)
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
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return -EINVAL;
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}
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/* Clear related PD (Power-Down) bit of module to turn on clock */
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NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
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@ -51,8 +52,9 @@ static inline int npcx_clock_control_off(const struct device *dev,
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struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
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const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT)
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
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return -EINVAL;
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}
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/* Set related PD (Power-Down) bit of module to turn off clock */
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NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);
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@ -824,8 +824,9 @@ static int dma_iproc_pax_do_xfer(const struct device *dev,
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set_ring_active(pd, idx, true);
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ret = wait_for_pkt_completion(dev, idx, pl_len + 1);
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if (ret)
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if (ret) {
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goto err_ret;
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}
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ret = poll_on_write_sync(dev, ring);
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k_mutex_lock(&ring->lock, K_FOREVER);
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@ -413,10 +413,11 @@ static inline void set_ring_active(struct dma_iproc_pax_data *pd,
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uint32_t val;
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val = sys_read32(RM_RING_REG(pd, idx, RING_CONTROL));
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if (active)
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if (active) {
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val |= RING_CONTROL_ACTIVE;
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else
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} else {
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val &= ~RING_CONTROL_ACTIVE;
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}
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sys_write32(val, RM_RING_REG(pd, idx, RING_CONTROL));
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}
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@ -443,9 +444,9 @@ static int init_ring(struct dma_iproc_pax_data *pd, enum ring_idx idx)
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sys_write32(RING_CONTROL_FLUSH, RM_RING_REG(pd, idx,
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RING_CONTROL));
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do {
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if (sys_read32(RM_RING_REG(pd, idx, RING_FLUSH_DONE)) &
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RING_FLUSH_DONE_MASK)
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if (sys_read32(RM_RING_REG(pd, idx, RING_FLUSH_DONE)) & RING_FLUSH_DONE_MASK) {
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break;
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}
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k_busy_wait(1);
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} while (--timeout);
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@ -968,8 +969,9 @@ static int dma_iproc_pax_process_dma_blocks(const struct device *dev,
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config->channel_direction,
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block_config,
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&non_hdr_bd_count);
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if (ret)
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if (ret) {
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goto err;
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}
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block_config = block_config->next_block;
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}
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@ -228,10 +228,11 @@ static void espi_bus_cfg_update_isr(const struct device *dev)
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NPCX_ESPI_HOST_CH_EN(chan));
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evt.evt_details = BIT(chan);
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if (evt.evt_data)
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if (evt.evt_data) {
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inst->ESPICFG |= BIT(chan);
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else
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} else {
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inst->ESPICFG &= ~BIT(chan);
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}
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espi_send_callbacks(&data->callbacks, dev, evt);
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}
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@ -569,10 +570,11 @@ static int espi_npcx_send_vwire(const struct device *dev,
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/* Get wire field and set/clear wire bit */
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val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
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if (level)
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if (level) {
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val |= bitmask;
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else
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} else {
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val &= ~bitmask;
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}
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SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
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LOG_DBG("Send VW: VWEVSM%d 0x%08X", reg_idx, inst->VWEVSM[reg_idx]);
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@ -809,10 +809,11 @@ int npcx_host_periph_write_request(enum lpc_peripheral_opcode op,
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!IS_BIT_SET(inst_kbc->HICTRL, NPCX_HICTRL_OBFMIE)) {
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return -ENOTSUP;
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}
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if (data)
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if (data) {
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LOG_INF("%s: op 0x%x data %x", __func__, op, *data);
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else
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} else {
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LOG_INF("%s: op 0x%x only", __func__, op);
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}
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switch (op) {
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case E8042_WRITE_KB_CHAR:
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@ -1010,8 +1011,9 @@ int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
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ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
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&host_sub_cfg.clks_list[i]);
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if (ret < 0)
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if (ret < 0) {
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return ret;
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}
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}
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/* Configure EC legacy configuration IO base address to 0x4E. */
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@ -347,12 +347,13 @@ static int w5500_set_config(const struct device *dev,
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if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE) &&
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type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
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if (config->promisc_mode) {
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if (!(mode & BIT(mr)))
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if (!(mode & BIT(mr))) {
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return -EALREADY;
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}
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}
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/* clear */
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WRITE_BIT(mode, mr, 0);
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/* clear */
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WRITE_BIT(mode, mr, 0);
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} else {
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if (mode & BIT(mr)) {
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return -EALREADY;
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@ -260,25 +260,29 @@ static int phy_mii_cfg_link(const struct device *dev,
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return -EIO;
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}
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if (adv_speeds & LINK_FULL_10BASE_T)
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if (adv_speeds & LINK_FULL_10BASE_T) {
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anar_reg |= MII_ADVERTISE_10_FULL;
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else
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} else {
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anar_reg &= ~MII_ADVERTISE_10_FULL;
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}
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if (adv_speeds & LINK_HALF_10BASE_T)
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if (adv_speeds & LINK_HALF_10BASE_T) {
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anar_reg |= MII_ADVERTISE_10_HALF;
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else
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} else {
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anar_reg &= ~MII_ADVERTISE_10_HALF;
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}
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if (adv_speeds & LINK_FULL_100BASE_T)
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if (adv_speeds & LINK_FULL_100BASE_T) {
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anar_reg |= MII_ADVERTISE_100_FULL;
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else
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} else {
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anar_reg &= ~MII_ADVERTISE_100_FULL;
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}
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if (adv_speeds & LINK_HALF_100BASE_T)
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if (adv_speeds & LINK_HALF_100BASE_T) {
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anar_reg |= MII_ADVERTISE_100_HALF;
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else
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} else {
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anar_reg &= ~MII_ADVERTISE_100_HALF;
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}
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bmcr_reg |= MII_BMCR_AUTONEG_ENABLE;
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@ -50,8 +50,9 @@ static uint16_t phy_xlnx_gem_mdio_read(
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* current command.
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*/
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do {
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if (poll_cnt++ > 0)
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if (poll_cnt++ > 0) {
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k_busy_wait(100);
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}
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reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
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if (poll_cnt == 10) {
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@ -82,8 +83,9 @@ static uint16_t phy_xlnx_gem_mdio_read(
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*/
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poll_cnt = 0;
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do {
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if (poll_cnt++ > 0)
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if (poll_cnt++ > 0) {
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k_busy_wait(100);
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}
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reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
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if (poll_cnt == 10) {
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@ -127,8 +129,9 @@ static void phy_xlnx_gem_mdio_write(
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* current command.
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*/
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do {
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if (poll_cnt++ > 0)
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if (poll_cnt++ > 0) {
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k_busy_wait(100);
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}
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reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
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if (poll_cnt == 10) {
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@ -161,8 +164,9 @@ static void phy_xlnx_gem_mdio_write(
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*/
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poll_cnt = 0;
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do {
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if (poll_cnt++ > 0)
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if (poll_cnt++ > 0) {
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k_busy_wait(100);
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}
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reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
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if (poll_cnt == 10) {
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@ -114,8 +114,9 @@ static int write_dword(const struct device *dev, off_t offset, uint64_t val)
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* However, keeping that code make it compatible with both
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* mechanisms.
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*/
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while (LL_FLASH_IsActiveFlag_OperationSuspended())
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while (LL_FLASH_IsActiveFlag_OperationSuspended()) {
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;
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}
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/* Enter critical section */
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key = irq_lock();
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@ -250,8 +251,9 @@ static int erase_page(const struct device *dev, uint32_t page)
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* However, keeping that code make it compatible with both
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* mechanisms.
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*/
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while (LL_FLASH_IsActiveFlag_OperationSuspended())
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while (LL_FLASH_IsActiveFlag_OperationSuspended()) {
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;
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}
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/* Enter critical section */
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key = irq_lock();
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@ -370,10 +370,11 @@ static int gpio_ite_configure(const struct device *dev,
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* Select open drain first, so that we don't glitch the signal
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* when changing the line to an output.
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*/
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if (flags & GPIO_OPEN_DRAIN)
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if (flags & GPIO_OPEN_DRAIN) {
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*reg_gpotr |= mask;
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else
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} else {
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*reg_gpotr &= ~mask;
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}
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/* 1.8V or 3.3V */
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reg_1p8v = &IT8XXX2_GPIO_GCRX(
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@ -396,10 +397,11 @@ static int gpio_ite_configure(const struct device *dev,
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/* If output, set level before changing type to an output. */
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH)
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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*reg_gpdr |= mask;
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else if (flags & GPIO_OUTPUT_INIT_LOW)
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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*reg_gpdr &= ~mask;
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}
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}
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/* Set input or output. */
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@ -537,15 +539,17 @@ static int gpio_ite_pin_interrupt_configure(const struct device *dev,
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uint8_t wuc_mask = gpio_irqs[gpio_irq].wuc_mask;
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/* Set both edges interrupt. */
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if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH)
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if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
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*(wubemr(wuc_group)) |= wuc_mask;
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else
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} else {
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*(wubemr(wuc_group)) &= ~wuc_mask;
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}
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if (trig & GPIO_INT_TRIG_LOW)
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if (trig & GPIO_INT_TRIG_LOW) {
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*(wuemr(wuc_group)) |= wuc_mask;
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else
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} else {
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*(wuemr(wuc_group)) &= ~wuc_mask;
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}
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/*
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* Always write 1 to clear the WUC status register after
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* modifying edge mode selection register (WUBEMR and WUEMR).
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@ -138,10 +138,11 @@ static int gpio_lpc11u6x_pin_configure(const struct device *port,
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if (flags & GPIO_SINGLE_ENDED) {
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/* Open source mode is not supported. */
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if (flags & GPIO_LINE_OPEN_DRAIN)
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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func |= IOCON_PIO_OD(1);
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else
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} else {
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return -ENOTSUP;
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}
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}
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if (flags & GPIO_PULL_UP) {
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@ -370,23 +371,26 @@ static int gpio_lpc11u6x_pin_interrupt_configure(const struct device *port,
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/* Select edge interrupt mode. */
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pint_regs->isel &= ~BIT(irq);
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/* Enable interrupts on falling and/or rising edges. */
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if (trig & GPIO_INT_TRIG_LOW)
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if (trig & GPIO_INT_TRIG_LOW) {
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pint_regs->sienf |= BIT(irq);
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else
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} else {
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pint_regs->cienf |= BIT(irq);
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if (trig & GPIO_INT_TRIG_HIGH)
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}
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if (trig & GPIO_INT_TRIG_HIGH) {
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pint_regs->sienr |= BIT(irq);
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else
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||||
} else {
|
||||
pint_regs->cienr |= BIT(irq);
|
||||
}
|
||||
break;
|
||||
case GPIO_INT_MODE_LEVEL:
|
||||
/* Select level interrupt mode. */
|
||||
pint_regs->isel |= BIT(irq);
|
||||
/* Set active level. */
|
||||
if (trig & GPIO_INT_TRIG_LOW)
|
||||
if (trig & GPIO_INT_TRIG_LOW) {
|
||||
pint_regs->cienf |= BIT(irq);
|
||||
else
|
||||
} else {
|
||||
pint_regs->sienf |= BIT(irq);
|
||||
}
|
||||
/* Enable level interrupt. */
|
||||
pint_regs->sienr |= BIT(irq);
|
||||
break;
|
||||
|
|
|
@ -78,8 +78,9 @@ static void nct38xx_alert_worker(struct k_work *work)
|
|||
}
|
||||
}
|
||||
|
||||
if (alert & BIT(NCT38XX_REG_ALERT_VENDOR_DEFINDED_ALERT))
|
||||
if (alert & BIT(NCT38XX_REG_ALERT_VENDOR_DEFINDED_ALERT)) {
|
||||
nct38xx_gpio_alert_handler(config->nct38xx_dev[i]);
|
||||
}
|
||||
}
|
||||
/* While the interrupt signal is still active; we have more work to do. */
|
||||
} while (gpio_pin_get_dt(&config->irq_gpio));
|
||||
|
|
|
@ -49,8 +49,9 @@ struct gpio_npcx_data {
|
|||
/* Platform specific GPIO functions */
|
||||
const struct device *npcx_get_gpio_dev(int port)
|
||||
{
|
||||
if (port >= gpio_devs_count)
|
||||
if (port >= gpio_devs_count) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return gpio_devs[port];
|
||||
}
|
||||
|
@ -107,8 +108,9 @@ static int gpio_npcx_config(const struct device *dev,
|
|||
* after setting all other attributes, so as not to create a
|
||||
* temporary incorrect logic state 0:input 1:output
|
||||
*/
|
||||
if ((flags & GPIO_OUTPUT) == 0)
|
||||
if ((flags & GPIO_OUTPUT) == 0) {
|
||||
inst->PDIR &= ~mask;
|
||||
}
|
||||
|
||||
/*
|
||||
* If this IO pad is configured for low-voltage power supply, the GPIO
|
||||
|
@ -120,10 +122,11 @@ static int gpio_npcx_config(const struct device *dev,
|
|||
}
|
||||
|
||||
/* Select open drain 0:push-pull 1:open-drain */
|
||||
if ((flags & GPIO_OPEN_DRAIN) != 0)
|
||||
if ((flags & GPIO_OPEN_DRAIN) != 0) {
|
||||
inst->PTYPE |= mask;
|
||||
else
|
||||
} else {
|
||||
inst->PTYPE &= ~mask;
|
||||
}
|
||||
|
||||
/* Select pull-up/down of GPIO 0:pull-up 1:pull-down */
|
||||
if ((flags & GPIO_PULL_UP) != 0) {
|
||||
|
@ -138,14 +141,16 @@ static int gpio_npcx_config(const struct device *dev,
|
|||
}
|
||||
|
||||
/* Set level 0:low 1:high */
|
||||
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0)
|
||||
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
|
||||
inst->PDOUT |= mask;
|
||||
else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0)
|
||||
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
|
||||
inst->PDOUT &= ~mask;
|
||||
}
|
||||
|
||||
/* Configure pin as output, if requested 0:input 1:output */
|
||||
if ((flags & GPIO_OUTPUT) != 0)
|
||||
if ((flags & GPIO_OUTPUT) != 0) {
|
||||
inst->PDIR |= mask;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -274,8 +279,9 @@ static int gpio_npcx_manage_callback(const struct device *dev,
|
|||
int pin = find_lsb_set(callback->pin_mask) - 1;
|
||||
|
||||
/* pin_mask should not be zero */
|
||||
if (pin < 0)
|
||||
if (pin < 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Has the IO pin valid MIWU input source? */
|
||||
if (config->wui_maps[pin].table == NPCX_MIWU_TABLE_NONE) {
|
||||
|
|
|
@ -292,8 +292,9 @@ static int enhanced_i2c_error(const struct device *dev)
|
|||
data->err = i2c_str & E_HOSTA_ANY_ERROR;
|
||||
/* device does not respond ACK */
|
||||
} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
|
||||
if (IT8XXX2_I2C_CTR(base) & E_ACK)
|
||||
if (IT8XXX2_I2C_CTR(base) & E_ACK) {
|
||||
data->err = E_HOSTA_ACK;
|
||||
}
|
||||
}
|
||||
|
||||
return data->err;
|
||||
|
|
|
@ -177,8 +177,9 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
|
|||
next_msg_flags = &(next->flags);
|
||||
}
|
||||
ret = i2c_stm32_transaction(dev, *current, next_msg_flags, slave);
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
break;
|
||||
}
|
||||
current++;
|
||||
num_msgs--;
|
||||
}
|
||||
|
|
|
@ -514,8 +514,9 @@ static void i2c_ctrl_handle_write_int_event(const struct device *dev)
|
|||
size_t tx_avail = MIN(tx_remain, i2c_ctrl_fifo_tx_avail(dev));
|
||||
|
||||
LOG_DBG("tx remains %d, avail %d", tx_remain, tx_avail);
|
||||
for (int i = 0U; i < tx_avail; i++)
|
||||
for (int i = 0U; i < tx_avail; i++) {
|
||||
i2c_ctrl_fifo_write(dev, *(data->ptr_msg++));
|
||||
}
|
||||
|
||||
/* Is there any remaining bytes? */
|
||||
if (data->ptr_msg == data->msg->buf + data->msg->len) {
|
||||
|
@ -926,9 +927,9 @@ static int i2c_ctrl_init(const struct device *dev)
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
if (i2c_rate == 15000000)
|
||||
if (i2c_rate == 15000000) {
|
||||
data->ptr_speed_confs = npcx_15m_speed_confs;
|
||||
else if (i2c_rate == 20000000) {
|
||||
} else if (i2c_rate == 20000000) {
|
||||
data->ptr_speed_confs = npcx_20m_speed_confs;
|
||||
} else {
|
||||
LOG_ERR("Unsupported apb2/3 freq for %s.", dev->name);
|
||||
|
|
|
@ -60,8 +60,9 @@ static int gic_wait_rwp(uint32_t intid)
|
|||
rwp_mask = BIT(GICD_CTLR_RWP);
|
||||
}
|
||||
|
||||
while (sys_read32(base) & rwp_mask)
|
||||
while (sys_read32(base) & rwp_mask) {
|
||||
;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -257,12 +258,14 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
|
|||
*/
|
||||
static void gicv3_rdist_enable(mem_addr_t rdist)
|
||||
{
|
||||
if (!(sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
|
||||
if (!(sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))) {
|
||||
return;
|
||||
}
|
||||
|
||||
sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
|
||||
while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
|
||||
while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GIC_V3_ITS
|
||||
|
|
|
@ -136,8 +136,9 @@ static void intc_miwu_isr_pri(int wui_table, int wui_group)
|
|||
uint8_t mask = NPCX_WKPND(base, wui_group) & NPCX_WKEN(base, wui_group);
|
||||
|
||||
/* Clear pending bits before dispatch ISR */
|
||||
if (mask)
|
||||
if (mask) {
|
||||
NPCX_WKPCL(base, wui_group) = mask;
|
||||
}
|
||||
|
||||
for (wui_bit = 0; wui_bit < 8; wui_bit++) {
|
||||
if (mask & BIT(wui_bit)) {
|
||||
|
|
|
@ -135,8 +135,9 @@ static void swerv_pic_irq_handler(const void *arg)
|
|||
|
||||
/* Call the corresponding IRQ handler in _sw_isr_table */
|
||||
ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
|
||||
if (ite->isr)
|
||||
if (ite->isr) {
|
||||
ite->isr(ite->arg);
|
||||
}
|
||||
|
||||
swerv_pic_write(SWERV_PIC_meigwclr(irq), 0);
|
||||
}
|
||||
|
|
|
@ -99,14 +99,15 @@ static void drive_keyboard_column(const struct device *dev, int col)
|
|||
int mask;
|
||||
|
||||
/* Tri-state all outputs */
|
||||
if (col == KEYBOARD_COLUMN_DRIVE_NONE)
|
||||
if (col == KEYBOARD_COLUMN_DRIVE_NONE) {
|
||||
mask = 0x3ffff;
|
||||
/* Assert all outputs */
|
||||
else if (col == KEYBOARD_COLUMN_DRIVE_ALL)
|
||||
} else if (col == KEYBOARD_COLUMN_DRIVE_ALL) {
|
||||
mask = 0;
|
||||
/* Assert a single output */
|
||||
else
|
||||
} else {
|
||||
mask = 0x3ffff ^ BIT(col);
|
||||
}
|
||||
|
||||
/* Set KSO[17:0] output data */
|
||||
inst->KBS_KSOL = (uint8_t) (mask & 0xff);
|
||||
|
@ -241,8 +242,9 @@ static bool check_key_events(const struct device *dev)
|
|||
uint8_t row_changed = 0U;
|
||||
uint8_t deb_col;
|
||||
|
||||
if (++data->scan_cycles_idx >= SCAN_OCURRENCES)
|
||||
if (++data->scan_cycles_idx >= SCAN_OCURRENCES) {
|
||||
data->scan_cycles_idx = 0U;
|
||||
}
|
||||
|
||||
data->scan_clk_cycle[data->scan_cycles_idx] = cycles_now;
|
||||
|
||||
|
@ -398,8 +400,9 @@ void polling_task(const struct device *dev, void *dummy2, void *dummy3)
|
|||
CLOCK_32K_HW_CYCLES_TO_US(cycles_delta);
|
||||
|
||||
/* Override wait_period in case it's less than 1000 us */
|
||||
if (wait_period < MS_TO_US)
|
||||
if (wait_period < MS_TO_US) {
|
||||
wait_period = MS_TO_US;
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait period results in a larger number when
|
||||
|
|
|
@ -4990,24 +4990,24 @@ static int compare_versions(char *v1, const char *v2)
|
|||
ver2 = strtoul(v2, &tail2, 10);
|
||||
|
||||
/* if numbers differ, then set the result */
|
||||
if (ver1 < ver2)
|
||||
if (ver1 < ver2) {
|
||||
result = -1;
|
||||
else if (ver1 > ver2)
|
||||
} else if (ver1 > ver2) {
|
||||
result = 1;
|
||||
else {
|
||||
} else {
|
||||
/* if numbers are the same, go to next level */
|
||||
v1 = tail1;
|
||||
v2 = tail2;
|
||||
/* if we reach the end of both, then they are identical */
|
||||
if (*v1 == '\0' && *v2 == '\0')
|
||||
if (*v1 == '\0' && *v2 == '\0') {
|
||||
break;
|
||||
/* if we reach the end of one only, it is the smaller */
|
||||
else if (*v1 == '\0')
|
||||
} else if (*v1 == '\0') {
|
||||
result = -1;
|
||||
else if (*v2 == '\0')
|
||||
} else if (*v2 == '\0') {
|
||||
result = 1;
|
||||
/* not at end ... so far they match so keep going */
|
||||
else {
|
||||
} else {
|
||||
v1++;
|
||||
v2++;
|
||||
}
|
||||
|
|
|
@ -97,8 +97,9 @@ static inline int find_len(char *data)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
if (data[i] == '\r')
|
||||
if (data[i] == '\r') {
|
||||
break;
|
||||
}
|
||||
|
||||
buf[i] = data[i];
|
||||
}
|
||||
|
|
|
@ -709,13 +709,15 @@ static int offload_getaddrinfo(const char *node, const char *service,
|
|||
|
||||
if (service) {
|
||||
port = atoi(service);
|
||||
if (port < 1 || port > USHRT_MAX)
|
||||
if (port < 1 || port > USHRT_MAX) {
|
||||
return DNS_EAI_SERVICE;
|
||||
}
|
||||
}
|
||||
|
||||
if (port > 0U) {
|
||||
if (dns_result.ai_family == AF_INET)
|
||||
if (dns_result.ai_family == AF_INET) {
|
||||
net_sin(&dns_result_addr)->sin_port = htons(port);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if node is an IP address */
|
||||
|
@ -1809,14 +1811,15 @@ int mdm_sim7080_ftp_get_start(const char *server, const char *user, const char *
|
|||
*/
|
||||
static uint8_t mdm_pdu_decode_ascii(char byte)
|
||||
{
|
||||
if ((byte >= '0') && (byte <= '9'))
|
||||
if ((byte >= '0') && (byte <= '9')) {
|
||||
return byte - '0';
|
||||
else if ((byte >= 'A') && (byte <= 'F'))
|
||||
} else if ((byte >= 'A') && (byte <= 'F')) {
|
||||
return byte - 'A' + 10;
|
||||
else if ((byte >= 'a') && (byte <= 'f'))
|
||||
} else if ((byte >= 'a') && (byte <= 'f')) {
|
||||
return byte - 'a' + 10;
|
||||
else
|
||||
} else {
|
||||
return 255;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -163,8 +163,9 @@ static int iproc_pcie_register_reset_cb(const struct device *dev,
|
|||
{
|
||||
struct iproc_pcie_ep_ctx *ctx = dev->data;
|
||||
|
||||
if (reset < PCIE_PERST || reset >= PCIE_RESET_MAX)
|
||||
if (reset < PCIE_PERST || reset >= PCIE_RESET_MAX) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
LOG_DBG("Registering the callback for reset %d", reset);
|
||||
ctx->reset_cb[reset] = cb;
|
||||
|
|
|
@ -90,24 +90,27 @@ static int pcie_ecam_init(const struct device *dev)
|
|||
data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_IO].bus_start < 0x1000)
|
||||
if (data->regions[PCIE_REGION_IO].bus_start < 0x1000) {
|
||||
data->regions[PCIE_REGION_IO].allocation_offset = 0x1000;
|
||||
}
|
||||
break;
|
||||
case 0x02:
|
||||
data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr;
|
||||
data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000)
|
||||
if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000) {
|
||||
data->regions[PCIE_REGION_MEM].allocation_offset = 0x1000;
|
||||
}
|
||||
break;
|
||||
case 0x03:
|
||||
data->regions[PCIE_REGION_MEM64].bus_start = cfg->ranges[i].pcie_bus_addr;
|
||||
data->regions[PCIE_REGION_MEM64].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_MEM64].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000)
|
||||
if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000) {
|
||||
data->regions[PCIE_REGION_MEM64].allocation_offset = 0x1000;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -197,8 +200,9 @@ static bool pcie_ecam_region_allocate_type(struct pcie_ecam_data *data, pcie_bdf
|
|||
addr = (((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) |
|
||||
((bar_size) - 1)) + 1;
|
||||
|
||||
if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size)
|
||||
if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size) {
|
||||
return false;
|
||||
}
|
||||
|
||||
*bar_bus_addr = addr;
|
||||
data->regions[type].allocation_offset = addr - data->regions[type].bus_start + bar_size;
|
||||
|
@ -291,8 +295,9 @@ static bool pcie_ecam_region_translate(const struct device *dev, pcie_bdf_t bdf,
|
|||
enum pcie_region_type type;
|
||||
|
||||
/* Means it hasn't been allocated */
|
||||
if (!bar_bus_addr)
|
||||
if (!bar_bus_addr) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||
|
||||
(data->regions[PCIE_REGION_MEM64].size &&
|
||||
|
|
|
@ -42,8 +42,9 @@ int pm_cpu_off(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (psci_data.conduit == SMCCC_CONDUIT_NONE)
|
||||
if (psci_data.conduit == SMCCC_CONDUIT_NONE) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = psci_data.invoke_psci_fn(PSCI_0_2_FN_CPU_OFF, 0, 0, 0);
|
||||
|
||||
|
@ -55,8 +56,9 @@ int pm_cpu_on(unsigned long cpuid,
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (psci_data.conduit == SMCCC_CONDUIT_NONE)
|
||||
if (psci_data.conduit == SMCCC_CONDUIT_NONE) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = psci_data.invoke_psci_fn(PSCI_FN_NATIVE(0_2, CPU_ON), cpuid,
|
||||
(unsigned long) entry_point, 0);
|
||||
|
|
|
@ -44,8 +44,9 @@ static int ps2_npcx_ch_configure(const struct device *dev,
|
|||
|
||||
ret = ps2_npcx_ctrl_configure(config->ps2_ctrl, config->channel_id,
|
||||
callback_isr);
|
||||
if (ret != 0)
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ps2_npcx_ctrl_enable_interface(config->ps2_ctrl,
|
||||
config->channel_id, 1);
|
||||
|
|
|
@ -290,8 +290,9 @@ static void ps2_npcx_ctrl_isr(const struct device *dev)
|
|||
|
||||
LOG_DBG("Recv:0x%02x", data_in);
|
||||
callback = data->callback_isr[active_ch];
|
||||
if (callback != NULL)
|
||||
if (callback != NULL) {
|
||||
callback(dev, data_in);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -53,8 +53,9 @@ static struct pwm_ledc_esp32_channel_config *get_channel_config(const struct dev
|
|||
(struct pwm_ledc_esp32_config *) dev->config;
|
||||
|
||||
for (uint8_t i = 0; i < config->channel_len; i++) {
|
||||
if (config->channel_config[i].idx == channel_id)
|
||||
if (config->channel_config[i].idx == channel_id) {
|
||||
return &config->channel_config[i];
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
@ -159,12 +160,14 @@ static int pwm_led_esp32_timer_config(struct pwm_ledc_esp32_channel_config *chan
|
|||
*/
|
||||
|
||||
channel->clock_src = LEDC_APB_CLK;
|
||||
if (!pwm_led_esp32_calculate_max_resolution(channel))
|
||||
if (!pwm_led_esp32_calculate_max_resolution(channel)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
channel->clock_src = LEDC_REF_TICK;
|
||||
if (!pwm_led_esp32_calculate_max_resolution(channel))
|
||||
if (!pwm_led_esp32_calculate_max_resolution(channel)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
@ -685,8 +685,9 @@ int iis2iclx_shub_get_idx(const struct device *dev, enum sensor_channel type)
|
|||
for (n = 0; n < data->num_ext_dev; n++) {
|
||||
sp = &iis2iclx_shub_slist[data->shub_ext[n]];
|
||||
|
||||
if (sp->type == type)
|
||||
if (sp->type == type) {
|
||||
return n;
|
||||
}
|
||||
}
|
||||
|
||||
return -ENOTSUP;
|
||||
|
@ -729,8 +730,9 @@ int iis2iclx_shub_config(const struct device *dev, enum sensor_channel chan,
|
|||
for (n = 0; n < data->num_ext_dev; n++) {
|
||||
sp = &iis2iclx_shub_slist[data->shub_ext[n]];
|
||||
|
||||
if (sp->type == chan)
|
||||
if (sp->type == chan) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (n == data->num_ext_dev) {
|
||||
|
@ -755,8 +757,9 @@ int iis2iclx_shub_init(const struct device *dev)
|
|||
|
||||
LOG_INF("shub: start sensorhub for %s", dev->name);
|
||||
for (n = 0; n < ARRAY_SIZE(iis2iclx_shub_slist); n++) {
|
||||
if (data->num_ext_dev >= IIS2ICLX_SHUB_MAX_NUM_SLVS)
|
||||
if (data->num_ext_dev >= IIS2ICLX_SHUB_MAX_NUM_SLVS) {
|
||||
break;
|
||||
}
|
||||
|
||||
chip_id = 0;
|
||||
sp = &iis2iclx_shub_slist[n];
|
||||
|
|
|
@ -655,8 +655,9 @@ int ism330dhcx_shub_get_idx(enum sensor_channel type)
|
|||
for (n = 0; n < num_ext_dev; n++) {
|
||||
sp = &ism330dhcx_shub_slist[shub_ext[n]];
|
||||
|
||||
if (sp->type == type)
|
||||
if (sp->type == type) {
|
||||
return n;
|
||||
}
|
||||
}
|
||||
|
||||
return -ENOTSUP;
|
||||
|
@ -697,8 +698,9 @@ int ism330dhcx_shub_config(const struct device *dev, enum sensor_channel chan,
|
|||
for (n = 0; n < num_ext_dev; n++) {
|
||||
sp = &ism330dhcx_shub_slist[shub_ext[n]];
|
||||
|
||||
if (sp->type == chan)
|
||||
if (sp->type == chan) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (n == num_ext_dev) {
|
||||
|
@ -721,8 +723,9 @@ int ism330dhcx_shub_init(const struct device *dev)
|
|||
struct ism330dhcx_shub_slist *sp;
|
||||
|
||||
for (n = 0; n < ARRAY_SIZE(ism330dhcx_shub_slist); n++) {
|
||||
if (num_ext_dev >= ISM330DHCX_SHUB_MAX_NUM_SLVS)
|
||||
if (num_ext_dev >= ISM330DHCX_SHUB_MAX_NUM_SLVS) {
|
||||
break;
|
||||
}
|
||||
|
||||
chip_id = 0;
|
||||
sp = &ism330dhcx_shub_slist[n];
|
||||
|
|
|
@ -682,8 +682,9 @@ int lsm6dso_shub_get_idx(const struct device *dev, enum sensor_channel type)
|
|||
for (n = 0; n < data->num_ext_dev; n++) {
|
||||
sp = &lsm6dso_shub_slist[data->shub_ext[n]];
|
||||
|
||||
if (sp->type == type)
|
||||
if (sp->type == type) {
|
||||
return n;
|
||||
}
|
||||
}
|
||||
|
||||
LOG_ERR("shub: dev %s type %d not supported", dev->name, type);
|
||||
|
@ -728,8 +729,9 @@ int lsm6dso_shub_config(const struct device *dev, enum sensor_channel chan,
|
|||
for (n = 0; n < data->num_ext_dev; n++) {
|
||||
sp = &lsm6dso_shub_slist[data->shub_ext[n]];
|
||||
|
||||
if (sp->type == chan)
|
||||
if (sp->type == chan) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (n == data->num_ext_dev) {
|
||||
|
@ -754,8 +756,9 @@ int lsm6dso_shub_init(const struct device *dev)
|
|||
|
||||
LOG_INF("shub: start sensorhub for %s", dev->name);
|
||||
for (n = 0; n < ARRAY_SIZE(lsm6dso_shub_slist); n++) {
|
||||
if (data->num_ext_dev >= LSM6DSO_SHUB_MAX_NUM_SLVS)
|
||||
if (data->num_ext_dev >= LSM6DSO_SHUB_MAX_NUM_SLVS) {
|
||||
break;
|
||||
}
|
||||
|
||||
chip_id = 0;
|
||||
sp = &lsm6dso_shub_slist[n];
|
||||
|
|
|
@ -33,8 +33,9 @@ static int get_channels(const struct device *dev, ...)
|
|||
int err;
|
||||
|
||||
chan = va_arg(ptr, int);
|
||||
if (chan == -1)
|
||||
if (chan == -1) {
|
||||
break;
|
||||
}
|
||||
val = va_arg(ptr, struct sensor_value *);
|
||||
err = sensor_channel_get(dev, chan, val);
|
||||
if (err < 0) {
|
||||
|
|
|
@ -25,8 +25,9 @@ int vcnl4040_read(const struct device *dev, uint8_t reg, uint16_t *out)
|
|||
ret = i2c_write_read_dt(&config->i2c,
|
||||
®, sizeof(reg), buff, sizeof(buff));
|
||||
|
||||
if (!ret)
|
||||
if (!ret) {
|
||||
*out = sys_get_le16(buff);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -217,9 +217,9 @@ static bool pl011_is_readable(const struct device *dev)
|
|||
struct pl011_data *data = dev->data;
|
||||
|
||||
if (!data->sbsa &&
|
||||
(!(get_uart(dev)->cr & PL011_CR_UARTEN) ||
|
||||
!(get_uart(dev)->cr & PL011_CR_RXE)))
|
||||
(!(get_uart(dev)->cr & PL011_CR_UARTEN) || !(get_uart(dev)->cr & PL011_CR_RXE))) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U;
|
||||
}
|
||||
|
@ -422,8 +422,9 @@ static int pl011_init(const struct device *dev)
|
|||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
config->irq_config_func(dev);
|
||||
#endif
|
||||
if (!data->sbsa)
|
||||
if (!data->sbsa) {
|
||||
pl011_enable(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -145,9 +145,9 @@ static inline void mss_qspi_transmit_x8(const struct device *dev, uint32_t len)
|
|||
skips &= ~MSS_QSPI_CONTROL_FLAGSX4;
|
||||
mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);
|
||||
for (count = 0; count < len; ++count) {
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS)
|
||||
& MSS_QSPI_STATUS_TXFIFOFULL)
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {
|
||||
;
|
||||
}
|
||||
if (spi_context_tx_buf_on(ctx)) {
|
||||
mss_qspi_write(s, ctx->tx_buf[0], MSS_QSPI_REG_TX_DATA);
|
||||
spi_context_update_tx(ctx, 1, 1);
|
||||
|
@ -166,9 +166,9 @@ static inline void mss_qspi_transmit_x32(const struct device *dev, uint32_t len)
|
|||
ctrl |= MSS_QSPI_CONTROL_FLAGSX4;
|
||||
mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);
|
||||
for (count = 0; count < len / 4; ++count) {
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS)
|
||||
& MSS_QSPI_STATUS_TXFIFOFULL)
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_TXFIFOFULL) {
|
||||
;
|
||||
}
|
||||
if (spi_context_tx_buf_on(ctx)) {
|
||||
wdata = UNALIGNED_GET((uint32_t *)(ctx->tx_buf));
|
||||
mss_qspi_write(s, wdata, MSS_QSPI_REG_X4_TX_DATA);
|
||||
|
@ -188,9 +188,9 @@ static inline void mss_qspi_receive_x32(const struct device *dev, uint32_t len)
|
|||
ctrl |= MSS_QSPI_CONTROL_FLAGSX4;
|
||||
mss_qspi_write(s, ctrl, MSS_QSPI_REG_CONTROL);
|
||||
for (count = 0; count < len / 4; ++count) {
|
||||
while ((mss_qspi_read(s, MSS_QSPI_REG_STATUS)
|
||||
& MSS_QSPI_STATUS_RXFIFOEMPTY))
|
||||
while ((mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY)) {
|
||||
;
|
||||
}
|
||||
if (spi_context_rx_buf_on(ctx)) {
|
||||
temp = mss_qspi_read(s, MSS_QSPI_REG_X4_RX_DATA);
|
||||
UNALIGNED_PUT(temp, (uint32_t *)ctx->rx_buf);
|
||||
|
@ -210,9 +210,9 @@ static inline void mss_qspi_receive_x8(const struct device *dev, uint32_t len)
|
|||
rdata &= ~MSS_QSPI_CONTROL_FLAGSX4;
|
||||
mss_qspi_write(s, rdata, MSS_QSPI_REG_CONTROL);
|
||||
for (count = 0; count < len; ++count) {
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS)
|
||||
& MSS_QSPI_STATUS_RXFIFOEMPTY)
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY) {
|
||||
;
|
||||
}
|
||||
if (spi_context_rx_buf_on(ctx)) {
|
||||
rdata = mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);
|
||||
UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);
|
||||
|
@ -236,14 +236,16 @@ static inline void mss_qspi_config_frames(const struct device *dev,
|
|||
} else {
|
||||
skips |= ((total_bytes << MSS_QSPI_FRAMES_CMDBYTES) & MSS_QSPI_FRAMES_CMDBYTES_MSK);
|
||||
}
|
||||
if (mss_qspi_read(s, MSS_QSPI_REG_CONTROL) & MSS_QSPI_CONTROL_MODE0)
|
||||
if (mss_qspi_read(s, MSS_QSPI_REG_CONTROL) & MSS_QSPI_CONTROL_MODE0) {
|
||||
skips |= MSS_QSPI_FRAMES_QSPI;
|
||||
}
|
||||
|
||||
skips &= ~MSS_QSPI_FRAMES_IDLE_MSK;
|
||||
if (x8)
|
||||
if (x8) {
|
||||
skips |= MSS_QSPI_FRAMES_FLAGBYTE;
|
||||
else
|
||||
} else {
|
||||
skips |= MSS_QSPI_FRAMES_FLAGWORD;
|
||||
}
|
||||
|
||||
mss_qspi_write(s, skips, MSS_QSPI_REG_FRAMES);
|
||||
}
|
||||
|
@ -317,16 +319,19 @@ static inline void mss_qspi_receive(const struct device *dev)
|
|||
|
||||
rd_bytes = spi_context_longest_current_buf(ctx);
|
||||
if (rd_bytes) {
|
||||
if (rd_bytes >= 4)
|
||||
if (rd_bytes >= 4) {
|
||||
mss_qspi_receive_x32(dev, rd_bytes);
|
||||
}
|
||||
|
||||
skips = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
|
||||
skips &= ~MSS_QSPI_CONTROL_FLAGSX4;
|
||||
mss_qspi_write(s, skips, MSS_QSPI_REG_CONTROL);
|
||||
idx = (rd_bytes - (rd_bytes % 4u));
|
||||
for (; idx < rd_bytes; ++idx) {
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) & MSS_QSPI_STATUS_RXFIFOEMPTY)
|
||||
while (mss_qspi_read(s, MSS_QSPI_REG_STATUS) &
|
||||
MSS_QSPI_STATUS_RXFIFOEMPTY) {
|
||||
;
|
||||
}
|
||||
if (spi_context_rx_buf_on(ctx)) {
|
||||
rdata = mss_qspi_read(s, MSS_QSPI_REG_RX_DATA);
|
||||
UNALIGNED_PUT(rdata, (uint8_t *)ctx->rx_buf);
|
||||
|
@ -342,8 +347,9 @@ static inline int mss_qspi_clk_gen_set(const struct mss_qspi_config *s,
|
|||
uint32_t control = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
|
||||
uint32_t idx, clkrate, val = 0, speed;
|
||||
|
||||
if (spi_cfg->frequency > s->clock_freq)
|
||||
if (spi_cfg->frequency > s->clock_freq) {
|
||||
speed = s->clock_freq / 2;
|
||||
}
|
||||
|
||||
for (idx = 1; idx < 16; idx++) {
|
||||
clkrate = s->clock_freq / (2 * idx);
|
||||
|
@ -424,8 +430,9 @@ static void mss_qspi_interrupt(const struct device *dev)
|
|||
int intfield = mss_qspi_read(cfg, MSS_QSPI_REG_STATUS);
|
||||
int ienfield = mss_qspi_read(cfg, MSS_QSPI_REG_IEN);
|
||||
|
||||
if ((intfield & ienfield) == 0)
|
||||
if ((intfield & ienfield) == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (intfield & MSS_QSPI_IEN_TXDONE) {
|
||||
mss_qspi_write(cfg, MSS_QSPI_IEN_TXDONE, MSS_QSPI_REG_STATUS);
|
||||
|
|
|
@ -71,11 +71,12 @@ static int spi_oc_simple_configure(const struct spi_oc_simple_cfg *info,
|
|||
}
|
||||
|
||||
/* Set clock divider */
|
||||
for (i = 0; i < 12; i++)
|
||||
for (i = 0; i < 12; i++) {
|
||||
if ((config->frequency << (i + 1)) >
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
sys_write8((DIVIDERS[i] >> 4) & 0x3, SPI_OC_SIMPLE_SPER(info));
|
||||
spcr |= (DIVIDERS[i] & 0x3);
|
||||
|
|
|
@ -371,10 +371,11 @@ static int timer_init(enum ext_timer_idx ext_timer,
|
|||
IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
|
||||
IT8XXX2_EXT_ETXRST);
|
||||
|
||||
if (with_int == EXT_WITH_TIMER_INT)
|
||||
if (with_int == EXT_WITH_TIMER_INT) {
|
||||
irq_enable(irq_num);
|
||||
else
|
||||
} else {
|
||||
irq_disable(irq_num);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -131,8 +131,9 @@ static int sys_clock_driver_init(const struct device *dev)
|
|||
sys_write32(0xffffffff, TIMER_BASE_ADDR + CMCOR1_OFFSET);
|
||||
|
||||
/* Reset the counter for first channel, check WRFLG first */
|
||||
while (sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET) & CSR_WRITE_FLAG)
|
||||
while (sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET) & CSR_WRITE_FLAG) {
|
||||
;
|
||||
}
|
||||
sys_write32(0, TIMER_BASE_ADDR + CMCNT0_OFFSET);
|
||||
|
||||
for (i = 0; i < 1000; i++) {
|
||||
|
|
|
@ -264,9 +264,9 @@ static int wdt_npcx_disable(const struct device *dev)
|
|||
* Ensure we have waited at least 3 watchdog ticks before
|
||||
* stopping watchdog
|
||||
*/
|
||||
while (k_uptime_get() - data->last_watchdog_touch <
|
||||
NPCX_WDT_MIN_WND_TIME)
|
||||
while (k_uptime_get() - data->last_watchdog_touch < NPCX_WDT_MIN_WND_TIME) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop and unlock watchdog by writing 87h, 61h and 63h
|
||||
|
|
|
@ -355,8 +355,9 @@ static ssize_t eswifi_socket_recv(void *obj, void *buf, size_t max_len,
|
|||
} else {
|
||||
eswifi_unlock(eswifi);
|
||||
pkt = k_fifo_get(&socket->fifo, K_FOREVER);
|
||||
if (!pkt)
|
||||
if (!pkt) {
|
||||
return 0; /* EOF */
|
||||
}
|
||||
eswifi_lock(eswifi);
|
||||
}
|
||||
|
||||
|
|
|
@ -168,8 +168,9 @@ static void gop_eagain_retry(int cmd, struct gnttab_map_grant_ref *gref)
|
|||
|
||||
do {
|
||||
HYPERVISOR_grant_table_op(cmd, gref, 1);
|
||||
if (*status == GNTST_eagain)
|
||||
if (*status == GNTST_eagain) {
|
||||
k_sleep(K_MSEC(delay));
|
||||
}
|
||||
|
||||
delay += step;
|
||||
} while ((*status == GNTST_eagain) && (delay < GOP_RETRY_DELAY));
|
||||
|
|
|
@ -31,8 +31,9 @@ int hvm_get_parameter(int idx, uint64_t *value)
|
|||
xhv.index = idx;
|
||||
|
||||
ret = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv);
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
*value = xhv.value;
|
||||
return ret;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue