Adds a new spi_transcieve_cb API which enables asynchronous
SPI transactions with callback notification.
The exist spi_transcieve_async API remains and uses the new
spi_transcieve_cb API to provide a k_poll_signal notifier.
The driver API changes to provide a callback and userdata
parameter to async transcieve. All drivers in the tree
have been updated to the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add fundamental feature support for PL022 SPI peripheral.
This commit implements synchronous transfer with 8bit-MSB format.
Optional functions are not currently implemented yet.
- interrupt based transfer is not implemented yet.
- DMA transfer is not implemented yet.
- Slave mode is not implemented yet.
- Currently support only 8-bit data transfer.
Hardware limitation:
- LSB-first format is not supported by hardware.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This is a bug fix. A pointer to the spi configuration is not saved when
the spi driver is configured for slave operation and it can lead to
runtime errors.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
In order to work on a clock speed higher than 20 MHz, IO MUX is required.
Co-authored-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Signed-off-by: XiNGRZ Chan <hi@xingrz.me>
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds optional device tree property to specify a default character
to clock out when the TX buffer pointer is NULL. If the property is
not set the existing behavior (default char of 0x00) is used.
I verified the expected behavior using an i.MX RT685 board and
logic analyzer that the def-char character is transmitted when
TX buffer pointer is NULL.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
The commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
Update spi drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
Rework the <BUS>_emul_register calls to not pass the name param. The
name param is only used for logging and we can get it from the
struct <BUS>_emul instead.
Signed-off-by: Kumar Gala <galak@kernel.org>
Having a per-instance init function makes code cluttered and hard to
read. Just create a per-instance IRQ connect function (required to
resolve IRQ_CONNECT parameters at compile time).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using NRFX_SPI(S|M)_INSTANCE helper so that peripheral address from
Devicetree is used. We should not rely on HAL for hardware description
but Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move the RX (MISO) delaying capability information to Devicetree. It is
done using 2 properties:
- rx-delay-supported: enabled on SPI nodes that support delaying RX.
This property can be used by the driver to determine if this
capability is supported or not on a given instance.
- rx-delay: the actual RX delay value
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The maximum transfer buffer length is SoC specific, not instance
specific. This patch defines MAX_BUF_LEN at driver level in a SoC
specific manner instead of using HAL values that are instance specific
but that always take the same value depending on the SoC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The maximum transfer chunk length is SoC specific, not instance
specific. This patch defines MAX_CHUNK_LEN at driver level in a SoC
specific manner instead of using HAL values that are instance specific
but that always take the same value depending on the SoC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the overrun character in Devicetree. Since 0xFF is the most
common value, DT property contains such default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Devicetree is the natural place to describe hardware, so move the
maximum frequency the SPI can work with to Devicetree instead of relying
on values from HAL.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
DT nodes aren't guaranteed to define a label property. But emulated bus
controllers currently make use of this property to dispatch to the
associated emulator.
Have emulated bus controllers use DEVICE_DT_GET(node_id) to dispatch to
right target peripheral emulator. This also change makes emul_get_binding
and device_get_binding synonymous in behavior with respect to their
parameters.
This also strictly enforces a 1:1 correspondence between invocations of
DEVICE_DT_DEFINE and EMUL_DEFINE.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Allow emulator creators to write an init function that can be used
across multiple busses so as to reduce the boilerplate and cognitive
load in creating an emulator.
Part of this change includes allowing access to the emul struct from a
field in a {bus}_struct api (e.g. i2c_struct), which removes the need for
sporadic usages of CONTAINER_OF to access the emul struct.
Overall, this change simplifies and reduces the amount of boilerplate
code to get a device emulator up and running, thus reducing excise work
to writing tests.
TEST=twister on accel,espi, and eeprom drivers tests
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Run clang-format on all files touched by improved emulator API pull-request
that allowed access to the target device emulator from its bus api without
CONTAINER_OF usage.
drivers/i2c/i2c_emul.c
drivers/spi/spi_emul.c
include/zephyr/drivers/emul.h
include/zephyr/drivers/espi_emul.h
include/zephyr/drivers/i2c_emul.h
include/zephyr/drivers/spi_emul.h
subsys/emul/emul.c
subsys/emul/emul_bmi160.c
subsys/emul/espi/emul_espi_host.c
subsys/emul/i2c/emul_atmel_at24.c
TEST=twister on accel,espi, and eeprom drivers tests
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Implement support for half duplex communication in the bit bang SPI
driver. The SPI driver will use the MOSI pin is for both TX and RX
operations when using half duplex mode.
In half-duplex mode, the driver configures the MOSI pin as an input
pin for input only transactions. Transactions that are bidirectional
are forbidden. After an SPI transaction, the MOSI pin is left as an
input if it was an RX transaction or an output after a TX
transaction. Like before, the MOSI pin is initialized as an
(inactive) output pin when the bus is initialized.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.
This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
spi_context_cs_configure_all() is currently called from
spi_bitbang_transceive(). This causes a glitch when combined with
SPI_HOLD_ON_CS is used.
Move the initialization to spi_bitbang_init which is what the other
SPI drivers seem to do.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SPI bitbang driver doesn't correctly initialize the list of CS
GPIOs. As a consequence, SPI buses using the bitbang driver won't
drive CS low. Add the missing initialization.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.
This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds driver for the Microchip Polarfire SOC MSS QSPI
controller.
The interrupts of the MSS QSPI are routed through PLIC(Platform level
interrupt controller).
Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The SPI peripheral on SiFive parts uses FIFOs for Rx and Tx (FIFO size
undocumented, but empirically found to be 8 bytes on FE310, likely
identical on FU540 / FU740). Make use of these FIFOs in order to
continuiously feed Tx data as available.
Verified to transmit 1 MHz SPI @ 200 MHz coreclk / tlclk on FE310
continuously without downtime between frames.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
spi_context uses uint8_t buffers, and HW rxdata / txdata registers only
contain 8 bits of data (along with b31 full / empty flag), so uint8_t is
appropriate.
Suggested-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use the dedicated `DT_INST_STRING_TOKEN` macro instead of manually
retrieving `DT_DRV_INST`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add support for an alternate clock. If available,
alternate clock is enabled and used to get the
device clock rate.
Fixes#41650
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
