Build a combined mask from the tx_invert and rx_invert flags and pass it
to uart_hal_inverse_signal(). Only invoke the HAL call when the mask is
non-zero, preventing unintended inversions and eliminating redundant
calls when no inversion is requested.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add a log for the device name on bitrate changes, without this it's very
hard to understand what's going on in a system with multiple bridges.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Always return exit code 0 when cmd_uart_read stopped reading
data from UART. Instead, return with a error code in case
reading from the UART interface failed.
Currently, this command might return with exit code -1 because
uart_poll_in didn't return data and the read duration expired.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The source code is missing the Receive enable in serial
poll-in function so the status flag will never become affect
and data will never be read
Add the RE write before checking for receive status flag
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
...when FIFO is empty"
This reverts commit 47e43d552e.
This is breaking sample.sensor.shell.pytest where characters
are either missing or repeated when printing to the console.
Originally this is just for RISC-V with PLIC interrupt
controller. That was made more general to avoid having arch
specific code in a generic driver. And now it is breaking
on non-RISC-V platforms. Note that the QEMU RISC-V boards
all have PLIC as interrupt controller and are passing sensor
shell pytest without this workaround. So this does not seem
to be an issue with PLIC and NS16550. So revert the commit
for now.
Fixes#92187
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix issues that Renesas RZ boards cannot run the below serial
samples properly with sci and scif.
- `samples/subsys/console/echo`
- `samples/subsys/shell/shell_module`
The modification is to make the callback invoked in tei interrupt.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add PM hooks to release or reattach the serial ports from the bridge.
Does not save power per se but allows switch the lower level serial
ports for something else in runtime.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
CLOCK_CONTROL is required for fast instances of UART and COUNTER,
help select it when possible. The fast instances are UARTE120,
TIMER120 and TIMER121, and CLOCK_CONTROL is not supported for
CPUFLPR and CPUPPR even when the fast instances are used.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When uart_ns16550_irq_tx_enable() is called and the TX FIFO is already
empty, no new interrupt is generated, causing data transmission to stall
in some cases. This patch introduces a workaround to simulate an ISR
callback if the FIFO is empty when enabling the TX IRQ.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
It is not an error if the clock source for the UART is already
enabled. This may happen if a bootloader has used the UART and
not de-initialized it before booting the application.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This command waits for a given time (in seconds) and will continuously
poll from the UART device and print on the Shell console. This command
can be used to also test the RX line.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
clock control is required for "fast instances" so assert clock
is enabled alongside PM DEVICE RUNTIME. Update UART tests to
reflect this requirenment.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The UART_NRFX_UARTE_USE_CLOCK_CONTROL is no longer used and
incorrectly selects CLOCK_CONTROL if UARTE120 exists. Remove
it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The async_user_callback could be triggered from
both the DMA transfer complete interrupt and
a k_work queue timeout. Since the timeout runs
outside of an ISR context, it could be interrupted
by the DMA ISR. This might leads to a race condition
where both paths access and modify shared
DMA buffer state (offset and length) simultaneously,
causing data corruption or out-of-sequence processing.
Introduces proper synchronization to prevent concurrent
access to shared DMA buffer variables,
ensuring consistent and reliable data handling.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
When reception is restarted (STARTRX after ENDRX but no STOPRX) it is
possible that FRAMETIMEOUT countdown counter will not be started by
the first received byte if byte was already being transmitted when
STARTRX was called. If that is the only byte then it is expected that
timeout will be triggered but since FRAMETIMEOUT counter is not started
there is no FRAMETIMEOUT event which has short to STOPRX. This
situation will happen in case short buffers are used (< 5 bytes)
because then short ENDRX_STARTRX is not used then.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
PG142 from AMD specifically says the uartlite IP generates a
"rising-edge sensitive interrupt" when interrupts are enabled. When
using this IP on a ZynqMP platform with
CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get
configured correctly to detect these interrupts. Update driver to heed
the flags set by the interrupts property in the device tree.
Signed-off-by: Michael Estes <michael.estes@byteserv.io>
The uart_busy_set and uart_busy_clear are only used when runtime
pm is not enabled. So add #ifndef CONFIG_PM_DEVICE_RUNTIME to
enclose these two functions.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA request is asserted when there is space in the FIFO.
- A RX DMA request is asserted when data is in the FIFO.
When DMA is enabled for a peripheral, the DMA transfer completion is
signaled on the peripheral's interrupt only (here UART's interrupt).
It is not signaled on the DMA dedicated interrupt.
Also, when DMA is enabled for a peripheral, the DMA controller stops
the normal transfer interrupts for this peripheral from reaching the
NVIC (the interrupts are still reported in the interrupt registers of
the peripheral). Thus, when a large amount of data is transferred using
DMA, instead of receiving multiple interrupts from the peripheral as
data flows, the NVIC receives only one interrupt when the transfer
completes (unmasked peripheral error interrupts continue to be sent
to the NVIC).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Updated the Rx pin configuration in the lpuart_esp32 driver to fix a
typo and use correct MUX function.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit adds power management support to the UART driver for npck3
series chip.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds serial driver support for npck3.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Simplify the logic for the `uart_stm32_cfg2ll_databits` function
regarding `LL_USART_DATAWIDTH_9B` being defined or not.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Add support for getting to the lowest power mode when polling is
used with disable-rx property and interrupts are not used for
that UARTE. So far disabling of the UARTE peripheral was done in
the interrupt but in some cases interrupt may not be available
and in that case uart_poll_out shall wait until byte is transferred
and put UARTE into the lowest power state.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add the feature for the flexcomm uart to be able to be a wakeup source
from low power modes. To be able to do this on a relevant platform, the
DT node for the UART needs to have the wakeup-source property and define
a "sleep" clock. The details of handling the sleep clock and default
clock are still platform specific but handled by the clock control
driver of the platform, so that this code should be able to be
applicable to any platform that follows the same DT definition.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There is currently a bug where when entering low power modes, there is a
garbage character sent if the UART is in the middle of a transmit when
entering low power mode. This is because the fifo interrupt happens when
last character is pulled by transmitter from fifo and then we unlock PM
constraints at that moment, instead of waiting for actual transmitter to
become idle. Fix by adding work item to check for this when needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The USART is compatiable with the USART feature in sama7g5's Flexcom.
Update serial/usart_sam to support sama7g5.
Signed-off-by: Tony Han <tony.han@microchip.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Some SoCs generates unexpected RXTO event during restart.
Restart happens when ENDRX_STARTRX short is enabled and STOPRX
is triggered (via short or by CPU). STOPRX starts closing
procedure and ENDRX event is generated at some point which
triggers STARTRX and closing procedure is interrupted. RXTO
should not be triggered in that case. Due to internal timings
some SoC on fast UARTE instance will trigger RXTO followed
by RXSTARTED. This RXTO event shall be cleared as receiver is
actually restarted and not stopped.
Affected SoC is not in tree so Kconfig is added which enables
the workaround.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add initial support for TI MSPM0 UART with basic poll-in and poll-out
functionality.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Select SERIAL_SUPPORT_INTERRUPT for uart_bt, this is required to have
the interrupt API available.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
