uart drivers, that init in POST_KERNEL and
not in PRE_KERNEL_1 can't support
CONFIG_EARLY_CONSOLE, add a Kconfig for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Make uart_aesc_dev_cfg_##no "static const struct" instead of
"static struct" to move this struct into ROM. This reduces the
memory usage for this driver.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Replace nested MIN/MAX macro calls with the min3/max3 APIs which are
safer (evaluate arguments only once) and cleaner.
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add interrupt-driven API support to the esp32 lp_uart driver and make
RTS/CTS hardware flow control optional, enabled only when the device
tree sets hw-flow-control. Add a loopback property that ties TX to RX
inside the peripheral for self-test without external wiring.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the esp32 lp_uart driver to the esp32c5 and esp32p4. On the
esp32p4 the LP UART signals are routed through the LP GPIO matrix and
the controller is clocked from the precise XTAL_D2 source instead of
the uncalibrated RC_FAST, so the baud-rate framing is reliable.
Relax the fixed-pin bindings, describe the lp_uart node pins on the
c5/c6/p4 HP and LP cores, and extend the echo_ulp sample. Update
hal_espressif for the esp32p4 LP GPIO matrix and clock-tree helpers.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The `thread` field is not initialized, if it's being animated via
k_work_queue_run instead of k_work_queue_start.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Add UART driver support for NXP LPC84x series.
The driver supports polling and interrupt-driven modes with
runtime configuration. It integrates with Zephyr clock control
and pinctrl for device setup.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
The main goal of this change is being able to use counter_gecko_rtcc.c and
leuart_gecko.c on boards without an LFXO. This is the case for tyzs3.
The main changes are in soc/silabs/common, the rest is just to migrate all
of the boards.
This uses the device tree for clock-initialization only. I did not
implement a clock_control driver, because I don't see a need for that. The
drivers use CMU_ClockEnable, which abstracts away SoC differences already.
The config SOC_GECKO_HAS_HFRCO_FREQRANGE was removed, because:
- This can be detected via macros provided by gecko_sdk.
- There is an alternative to that API which wasn't implemented previously,
but is now (cmuHFRCOBand_*).
I don't own any of the boards except for tuya tyzs3, but did my best to
avoid mistakes. That being said, I found several issues, which were present
in some of the boards already:
- sltb004a: This board has a 38.4MHz HFXO crystal, but it was configured to
40MHz. I fixed that.
- tomu: This board uses HFRCO as it's HF clock, even though the SoC does
not support SOC_GECKO_HAS_HFRCO_FREQRANGE. So it was probably running at
the initial 14MHz instead.
- Many boards enabled leuart and rtcc (counter) peripherals, which need(ed)
LFXO, without ever enabling LFXO. These peripherals were probably not
working before this change.
Noteworthy finds:
- slwrb4321a: This board uses HFRCO as it's HF clock, but has a board.c
where it enables HFXO to use it as the RMII reference clock. I'm not sure
if it's okay to do that without calling CMU_HFXOInit first. I did not
modify that code to not change behavior that I don't understand.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
This commit fixes a bug where esp32 UART errors are cleared before they
can be read. Additionally, all line errors (such as break and FIFO
overflow) are now watched and reported.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
The USART init sequence configured BRR and CTLR1 (enabling the UART) and
only afterwards applied the pinctrl state. Reorder so that:
1. The clock is enabled.
2. The pinctrl state is applied before the peripheral is enabled.
3. CTLR1 is cleared first to ensure the UART is disabled while CTLR2/CTLR3
and the baud-rate divisor (BRR) are programmed, then CTLR1 is written
last to enable the UART with the final configuration.
Programming the control and baud-rate registers while the UART is disabled
and bringing up the pins before enabling avoids configuring the peripheral
in an undefined intermediate state. This is the ordering required by the
CH32H417 (QingKe V5F) and was regression-tested on a CH32V317 to confirm it
does not affect existing single-core parts.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
The UART bit clock is peripheral_clock / (divider * oversample), so the
driver must choose an oversample factor for the requested baud.
ifx_cat1_uart_set_baud() ranked candidates with ifx_uart_baud_diff(),
which returns the error as an integer percentage. At 100 MHz / 115200
every oversample (8-16) is under 1% and rounds to 0, so the first
candidate (oversample 8, -0.45%) always won, the least accurate option
with the smallest sampling margin.
Compare the error in absolute Hz instead. This selects oversample 14
(divider 62, 115207 baud, -0.006%), improving both accuracy and margin.
A zero divider is skipped to avoid divide-by-zero and the percentage
tolerance is kept as the validity check.
Assisted-by: Copilot:claude-opus-4.8
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add a wait for the Transmission Complete (TC) flag at the start of
mcux_lpuart_configure(). This prevents reconfiguration while the
hardware is still shifting out the final byte on the TX line.
Without this wait, uart_configure() could interrupt an ongoing
transmission, causing the last byte to not be fully sent on the UART
bus. This behavior was observed on NXP LPUART and tracked in issue
#109807.
Fixes#109807
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
Related to commit 01b611100c. When not using
the fifo, the renesas_ra_sci peripheral will resend the last transmitted
character if you manually clear the TDRE bit in the SSR status register.
This makes 'SSR &=' dangerous to use in the case where the TDRE bit is set
in between reading the register and updating it. The hardware manual says
that writing a zero clears status bits and writing a one is ignored, so the
update isn't needed, only write 0 to the bits that need to be cleared. Only
the error status bits need to be manually cleared, the RDRF bit is cleared
automatically by hardware.
Signed-off-by: Aaron Brice <aaron@embeddedts.com>
This commit fixes an issue where a framing error is never cleared
on the PL011 serial peripheral.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
- Kconfigs in modules/ should not define configs with an SOC_ prefix.
Furthermore, these options are SDK specific, not SoC specific.
- The simplicity_sdk configs do the same.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
The escape_conf bits reset to 1 and were left set, escaping 0xC0 and
0xDB on the async path even with SLIP off. Clear them, then enable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
`uart_irq_tx_ready` should report true if transmit is empty
and the transmit interrupt is enabled. This isn't documented in
drivers/uart.h but is required by code such
`subsys/modules/modbus_serial.c` and implemented in drivers such as
`uart_sam.c` and `uart_stm32.c`.
Fix.
Signed-off-by: Michael Hope <michaelh@juju.nz>
If UARTE instance is using GPPI during the initialization and GPPI is
using Ironside then that instance need to be initialized once Ironside
and GPPI is initialized. Delay initialization to POST_KERNEL and
derive init priority from Ironside call init priority (+2 as +1 is
used by GPPI).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Don't write to "DEVICE_MMIO_GET(dev)". Instead, store the register
base address in the data struct and use it for accessing the
registers later.
Also return a volatile pointer with DEV_UART and change
DEVICE_MMIO_NAMES_x to DEVICE_MMIO_x.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Spin on Transmitter Empty at the top of PM_DEVICE_ACTION_SUSPEND so an
in-flight byte finishes shifting before LD_ACTIVATE is cleared. Without
this, poll_out callers (printk, LOG_MODE_MINIMAL) get their last byte
cut off mid-shift on every suspend, producing garbled console output.
No-op when TX is already idle.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Use the `clocks` phandle to obtain the UART peripheral clock instead
of `clock-frequency` property. Update the binding and BCM2711 DTS
accordingly and rename the driver configuration field from
`clocks` to `pclk`.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add missing k_spin_unlock() on two error return paths in
uart_rza2m_scif_configure():
- Unsupported parity mode (default switch case)
- Baudrate configuration failure
Both paths returned without releasing the spinlock acquired earlier.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Add missing k_spin_unlock() and irq_unlock() in rzt2m_module_start()
error path. When interface_id >= 5 the function returned -ENOTSUP
without releasing either the spinlock or the IRQ lock.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
neorv32_uart_pm_action() returned -ENOTSUP for unsupported PM actions
without releasing the spinlock acquired at function entry. Restructure
to use a single unlock/return path at function exit.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Adds full interrupt-driven UART support behind
CONFIG_UART_INTERRUPT_DRIVEN. Implements the Zephyr UART interrupt
API (FIFO fill/read, TX/RX enable/disable, TX-complete detection,
pending check, callback set). Extends the register map with
tx_trigger, error_pending, and error_enable fields and adds RX FIFO
count and error bit masks. Adds SERIAL_SUPPORT_INTERRUPT to Kconfig.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Replace a COND_CODE_1() logic with use of DT_INST_PROP_OR() to get
the wakeup-line DT property for STM32 UART devices.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add support for interrup driven UART for the numicro uart driver
targeting the nuvoton m48x line.
This is mostly copied from the uart_numaker driver with some changes.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Use the new scc driver in the uart for the m48x numicro soc.
This removes quite a lot of calls into the nuvoton BSP and replaces
them with functions using the clock driver.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Flush tx and invalidate rx DMA buffers around UART async DMA
transfers so the CPU and DMA engine see coherent data on SoCs
with an L1 data cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add ESP32-P4 to the Espressif UART driver and the USB-serial-JTAG
backend, including the SoC-specific clock source selection
for the P4 UART HAL.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When enabling RX with a timeout of 0 in the mcux lpuart driver, the
driver silently skipped starting the async work timer, making partial
DMA transmissions fail. This commit handles the scenario by
immediatelly flushing the RX data, if any.
Make it so the async timer for TX is skipped if timeout is 0, disabling
TX timeout.
Signed-off-by: Guilherme Costa <guilhermecosta@stratioautomotive.com>
Compiling the mcux lpuart driver with format string validation led to a
runtime warning about pointer types. This commit fixes the issue by
casting the offending parameter to void * as recommended.
Signed-off-by: Guilherme Costa <guilhermecosta@stratioautomotive.com>
Update all drivers to use "flags" instead of "sense" when accessing
interrupt properties from device tree. This aligns with the updated
interrupt controller bindings that now consistently use "flags" as
the cell name for the IRQ type field.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Manually trigger TX IRQ when the buffer is empty to work around the
hardware limitation where the IRQ is not automatically generated.
Signed-off-by: Steven Chang <steven@ene.com.tw>
Add sleep retention support for UART driver. When peripheral
power down is enabled for light sleep, register data is lost,
so REGDMA backup is needed to mantein peripheral operational.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The four irq_{rx,tx}_{enable,disable} helpers each wrote a single
constant value to IER -- BIT(N) on enable, ~BIT(N) on disable. As
a result they did not toggle a single bit; they overwrote the
entire register. Two side effects:
* irq_tx_disable() set the RX-enable bit (because ~BIT(1) has bit 0
set), and vice versa. The expected sequence
irq_rx_disable(); irq_tx_disable();
ends with the RX bit on, even though the caller asked for both
channels to be quiesced.
* On the BCM283x mini-UART, the upper bits of IER carry FIFO-clear
shortcuts (see BCM2837 ARM Peripherals manual, "AUX_MU_IER_REG").
Writing 0xfffffffd or 0xfffffffe arbitrarily perturbs them.
Fix: each helper reads IER, sets or clears its own bit, writes
back. The TX/RX-enable side now also preserves the other channel's
state correctly.
Signed-off-by: Jonathan Elliot Peace <jep@alphabetiq.com>
The current implementation spins forever waiting for a character and
unconditionally returns 0. The uart_poll_in() API contract is that
the function returns -1 (or another negative value) immediately when
no character is currently available, and 0 only after writing a
received character to *c.
Without this, callers that use the canonical drain pattern --
while (uart_poll_in(dev, &c) == 0) {
;
}
-- hang. drivers/console/uart_console.c::console_input_init() does
exactly this when registering an input handler, so any application
that calls uart_register_input() (e.g. via Zephyr's console handler
subsystem) can deadlock at startup waiting on idle UART RX.
The fix is to test once and return -1 on the no-char path. The
"got a character" path is unchanged.
Signed-off-by: Jonathan Elliot Peace <jep@alphabetiq.com>
Add the option to explicitly request the HFXO while the UARTE peripheral
is active for nRF54L series devices. While the UARTE peripheral requests
a high frequency clock from the clock controller, both the HFINT and
HFXO oscillators satisfy this request. The problem is that the HFXO
oscillator is required to reach the highest bitrate accuracies (and
mitigate errata 30).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Re-added irq_update API for UART.
It is required to clean the FIFO status, which flushes
the content correctly.
Signed-off-by: Davide Di Lello <Davide.Dilello@Infineon.com>
