The LP_UART parameter configuration enabled the bus clock and
selected the source clock without asserting the reset register
in between. After a soft reset the LP_UART hardware could keep
stale state from the previous boot, leading to garbled output
until a power cycle cleared the registers.
Insert the missing lp_uart_ll_reset_register() between the bus
clock enable and the source clock selection.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Per the uart_polling header documentation, this API should
not block. Updating this API to simply check and return
instead of spinning until it gets a value.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
the return value of uart_irq_update() is not relevant,
therefore change it to void.
Also as most uart drivers don't need irq_update, make
it optional to implement this function in the driver.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove syscall from uart_irq_update() and
uart_irq_is_pending() as these are only allowed in
the interrupt.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
uart_rx_disable() may be called when RX was never enabled (e.g. test init).
Do not report this case as an error; log it at debug level instead.
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
Remove call of LPUART_Deinit() from mcux_lpuart_configure().
LPUART_Deinit() disables the LPUART clocks. If the configuration is not
supported, this may leave the LPUART in an uninitialized state with its
clocks disabled. Any subsequent access to LPUART registers can then
cause a hard fault.
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
NXP MCXC devices use the 4-channel DMA controller (nxp,4ch-dma) which
does not support eDMA-style "live reload" while the channel is busy.
This causes async RX double-buffering to fail when the next buffer is
preloaded from uart_rx_buf_rsp().
Introduce a per-instance rx_dma_live_reload flag derived from the DT DMA
controller compatible, and adjust async handling accordingly:
- Preload the next RX buffer only when live reload is supported.
- For nxp,4ch-dma, re-arm RX DMA from the DMA completion callback.
- Stop the TX DMA channel on completion to prevent repeated IRQs and treat
DMA errors as TX aborts.
- Set DMA block address adjustment fields explicitly for RX and TX.
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
Some devices do not provide LPUART FIFO support and therefore
lack LPUART_GetRxFifoCount(). Guard the FIFO-drain loop with
FSL_FEATURE_LPUART_HAS_FIFO and fall back to draining the RX data
register based on status flags.
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
MCUX LPUART async DMA configuration currently assumes eDMA-style DMA
specifiers (<mux source>). MCXC boards using nxp,4ch-dma describe DMA as
<channel source> instead.
Select the correct DT cell name based on the DMA controller compatible
and guard DMA config generation for instances without a 'dmas' property.
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
the boot banner is printed at the end of
the init process with
``SYS_INIT(boot_banner, APPLICATION, 0);``
we don't need the early console for it.
When CONFIG_EARLY_CONSOLE is enabled,
the console will init with PRE_KERNEL_1, otherwise
with POST_KERNEL. Both are before APPLICATION.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The UART driver's ISR could read the TC interrupt flag multiple times,
but doing so is unsafe as the interrupt flag could be clear during the
first read but set during the second, whereas the ISR expects the same
value all along.
Read the flag's status exactly once at the start of the ISR and use the
cached value in all checks instead of reading the hardware register.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use dt_compat_any_has_prop for CONFIG_UART_MCHP_DMA_DRIVEN to allow
mixed DMA/interrupt configurations. Added has_dma field and runtime
checks to select transfer mode per UART instance based on device tree
dmas property presence.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
For bsim targets MDK define (NRF_TIMERx) which is an address
of TIMER peripheral is not the same as register address for
timer node. Driver expects that address is set to the HW
peripheral address and it is later on converted to RAM
structure used by the bsim. Use address from the device tree
as it actually is set to the HW address, contrary to the
NRF_TIMERx macro which already points to the RAM structure
used by the simulator.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Convert the driver clock accesses to use the new generic API, so the
driver can be used on R-Car boards generations 3, 4 and 5 without changes.
This code has been tested on a Spider S4 and on an Ironhide X5H.
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
uart_cmsdk_apb_init() returns early when pinctrl_apply_state()
succeeds, because the return value check is wrong.
As a result, the rest of the UART initialization is skipped and
the device remains only partially initialized.
Ignore -ENOENT as intended, but continue init on success and
abort only on real pinctrl errors.
Signed-off-by: Andrei-Edward Popa <andreip@axonne.com>
The poll_in function doesn't return any error codes related to
the transmission itself. Call 'err_check' afterwarwds to make
sure no error flags are present.
Example: in case an FIFO overrun happens, poll_in would return
no data but this command should report the error.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
When the transmit FIFO is full and poll_out checks for availability,
it will read the register value only once and block forever. Make
the uart_aesc_regs struct volatile to read the FIFO availability
during each check.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
On STM32H5 / STM32U5 with GPDMA the USART can stop generating DMA RX
requests after uart_rx_disable() clears DMAR and DMAR is later re-enabled.
Toggling the USART enable (UE) before re-asserting DMAR resets the USART
internal state machine and allows RX DMA requests to resume.
Fixes: #101345
signed-off-by: Ashirwad Paswan <ashi06712@gmail.com>
Updated async mode to read the first byte manually and the
remaining bytes using dma as buffer overflow was happening
for rx enable with 1 byte.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
If CTS hardware flow control is in use, prevent an
infinite loop of callbacks.
Enable the CTS interrupt if TX is unavailable from
CTS blocking.
Signed-off-by: Ryan Erickson <ryan.erickson@ezurio.com>
Convert three NXP drivers from raw DT_REG_ADDR() register access
to the Zephyr device MMIO API (DEVICE_MMIO_ROM / DEVICE_MMIO_RAM /
DEVICE_MMIO_MAP):
With the MMIO API, the drivers create their own mapping at init time via
DEVICE_MMIO_MAP() thus the corresponding mmu_regions entries are removed
from the five NXP SoC files that carried them.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
nRF54x devices supports 4-9 bit frame size. Extend UART driver to
support data sizes supported by the Zephyr UART API (5-9 bits).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
The UARTE_GET_CUSTOM_BAUDRATE macro used an incorrect formula that
did not match the one specified in the nRF54x UARTE datasheet.
The correct formula is:
2^12 * floor(2^20 / round(f_PCLK / desired_baudrate))
Update the macro to match the datasheet formula, to reduce the
baudrate error for high-speed UART instances on nRF54x devices.
Signed-off-by: Ahmed Ahmed <ahmed.ahmed@dewinelabs.com>
Remove pinctrl sleep group init. Low power state for pinctrl will
be managed using harware feature.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Updated the interrupt handler to connect all interrupt lines added
in the corresponding sercom uart node.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Clock attach verification added previous to read flexcomm registers.
This ensures the flexcomm has a clock attached and is ready for
transmission, avoiding the system gets stuck in an infinite loop
while reading the registers.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
In uart_ra_sci_irq_tx_enable() it clears the Transmit Data Empty and
Transmit End flags. Doing this results in the uart re-sending the last
byte written to the TDR if the fifo is not being used. Avoid clearing the
status in the fifo-disabled case.
Signed-off-by: Aaron Brice <aaron@embeddedts.com>
Remove the duplicated ifx_cat1_get_hfclk_for_peri_group() function and
use version from shared header file.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
The low RX FIFO threshold of 1 could lead to issues during higher baud
rates, thus the threshold is increased and the RX Timeout feature on the
MSPM0 is introduced.
Signed-off-by: Jackson Farley <j-farley@ti.com>
The isr implementation would clear pending interrupts that had fired
since the first check for pending interrupts, leading to missed events.
This PR amends that issue and fixes typos in comparing IIDX types rather
than bitmasks to explicit comparisons
Signed-off-by: Jackson Farley <j-farley@ti.com>
PM suspend operation cannot be performed for UART using asynchronous
API is there are any active operations. Instead of asserting return
error.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The async mode ISR silently cleared RX error flags (overrun, parity,
framing, noise) without notifying the application. This violates the
Zephyr async UART API which requires a UART_RX_STOPPED event followed
by UART_RX_BUF_RELEASED and UART_RX_DISABLED.
Enable RX error interrupts alongside the idle-line interrupt, and
handle them in the ISR by reporting UART_RX_STOPPED with the
appropriate reason bitmask, then calling rx_disable() for the full
API-mandated teardown sequence.
Also set rx_dma_params.buf to NULL in rx_disable() after releasing
buffers, so stale pointers are not left behind.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Clear rx_dma_params.buf to NULL in mcux_lpuart_rx_disable() after
releasing all buffers. Without this, the stale pointer remains set
after RX teardown, which can cause subsequent checks against buf
to incorrectly assume RX is still active.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Extend UART and USB serial drivers to support ESP32-C5. Add UHCI0
compatibility macro since the ESP32-C5 HAL exports the UHCI
peripheral as UHCI instead of UHCI0.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Pass the function argument `dev` to the async callback instead of
`data->uart_dev`. The pointers are identical, but `dev` is already
available in this context, so it's clearer to use it directly.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
