Convert three NXP drivers from raw DT_REG_ADDR() register access
to the Zephyr device MMIO API (DEVICE_MMIO_ROM / DEVICE_MMIO_RAM /
DEVICE_MMIO_MAP):
With the MMIO API, the drivers create their own mapping at init time via
DEVICE_MMIO_MAP() thus the corresponding mmu_regions entries are removed
from the five NXP SoC files that carried them.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
nRF54x devices supports 4-9 bit frame size. Extend UART driver to
support data sizes supported by the Zephyr UART API (5-9 bits).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
The UARTE_GET_CUSTOM_BAUDRATE macro used an incorrect formula that
did not match the one specified in the nRF54x UARTE datasheet.
The correct formula is:
2^12 * floor(2^20 / round(f_PCLK / desired_baudrate))
Update the macro to match the datasheet formula, to reduce the
baudrate error for high-speed UART instances on nRF54x devices.
Signed-off-by: Ahmed Ahmed <ahmed.ahmed@dewinelabs.com>
Remove pinctrl sleep group init. Low power state for pinctrl will
be managed using harware feature.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Updated the interrupt handler to connect all interrupt lines added
in the corresponding sercom uart node.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Clock attach verification added previous to read flexcomm registers.
This ensures the flexcomm has a clock attached and is ready for
transmission, avoiding the system gets stuck in an infinite loop
while reading the registers.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
In uart_ra_sci_irq_tx_enable() it clears the Transmit Data Empty and
Transmit End flags. Doing this results in the uart re-sending the last
byte written to the TDR if the fifo is not being used. Avoid clearing the
status in the fifo-disabled case.
Signed-off-by: Aaron Brice <aaron@embeddedts.com>
Remove the duplicated ifx_cat1_get_hfclk_for_peri_group() function and
use version from shared header file.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
The low RX FIFO threshold of 1 could lead to issues during higher baud
rates, thus the threshold is increased and the RX Timeout feature on the
MSPM0 is introduced.
Signed-off-by: Jackson Farley <j-farley@ti.com>
The isr implementation would clear pending interrupts that had fired
since the first check for pending interrupts, leading to missed events.
This PR amends that issue and fixes typos in comparing IIDX types rather
than bitmasks to explicit comparisons
Signed-off-by: Jackson Farley <j-farley@ti.com>
PM suspend operation cannot be performed for UART using asynchronous
API is there are any active operations. Instead of asserting return
error.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The async mode ISR silently cleared RX error flags (overrun, parity,
framing, noise) without notifying the application. This violates the
Zephyr async UART API which requires a UART_RX_STOPPED event followed
by UART_RX_BUF_RELEASED and UART_RX_DISABLED.
Enable RX error interrupts alongside the idle-line interrupt, and
handle them in the ISR by reporting UART_RX_STOPPED with the
appropriate reason bitmask, then calling rx_disable() for the full
API-mandated teardown sequence.
Also set rx_dma_params.buf to NULL in rx_disable() after releasing
buffers, so stale pointers are not left behind.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Clear rx_dma_params.buf to NULL in mcux_lpuart_rx_disable() after
releasing all buffers. Without this, the stale pointer remains set
after RX teardown, which can cause subsequent checks against buf
to incorrectly assume RX is still active.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Extend UART and USB serial drivers to support ESP32-C5. Add UHCI0
compatibility macro since the ESP32-C5 HAL exports the UHCI
peripheral as UHCI instead of UHCI0.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Pass the function argument `dev` to the async callback instead of
`data->uart_dev`. The pointers are identical, but `dev` is already
available in this context, so it's clearer to use it directly.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add abstraction function to check the TX/RX fifo flags and enable/disable,
and redefine a few macros (like stop bits or data width) for STM32 HAL2.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Apply PINCTRL_STATE_SLEEP on suspend and PINCTRL_STATE_DEFAULT on resume
so that pin configuration is updated for low power modes.
Previously the suspend and resume actions were empty, leaving pins in
their active configuration during sleep. On SoCs like RW6xx where pad
control registers survive low power modes, this allos boards to define
sleep pinctrl states with appropriate pull or drive setting s to minimize
leakage.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
A lot of BeagleBoard.org boards contain SOCs with co-processors such as
M4F in AM62x (PocketBeagle 2 [0]), R5s in AM67A (BeagleY-AI [1]). In such
targets, the application is normally loaded by the Linux host using
remoteproc.
There have been some out of tree patches to have micropython and other
Zephyr applications output to allow having a console without requiring
manual connections. This patch attempts to provide a more concrete and
upstream way to have that functionality.
The implementation uses existing rpmsg service subsystem.
Only implemented poll_out
Tested on PocketBeagle 2 M4F core.
[0]: https://docs.zephyrproject.org/latest/boards/beagle/pocketbeagle_2/doc/index.html
[1]: https://docs.zephyrproject.org/latest/boards/beagle/beagley_ai/doc/index.html
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Enabling and disabling interrupts may happen concurrently from thread
and interrupt context. Add locks to synchronize the access to the ctrl
register.
This was observed to improve the stability of the zephyr,bt-hci-uart
driver when used with the cmsdk_apb uart driver.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Similar to the TX interrupt, the RX interrupt is also an edge interrupt
that only fires when a new bytes is received. When enabling the RX
interrupt, data may be already present in the RX FIFO. Call the
interrupt handler manually to start processing.
Also check if calling the interrupt handler is really required.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
irq_is_pending should not return 1 when interrupts are disabled through
irq_XX_disable. Check the interrupt enable bit before returning.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update the Infineon PDL UART driver to support Zephyr's standard
UART hardware flow control configuration.
Flow control is now derived from uart_config.flow_control allowing
applications to enable RTS/CTS using the generic UART API and
devicetree settings
configure the RTS rx fifo trigger level when flow control is enabled
Signed-off-by: Merin George <merin.george@infineon.com>
STANDBY state can place the peripheral into a
low‑power state, and transitioning to it before
a TX transmission completes may cause data loss
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
When UART_INTERRUPT_DRIVE, PM and UART_CONSOLE_INPUT_EXPIRED are all
defined the driver uses the device flags without the necessary declaratoins
or fetching the hardware register.
Signed-off-by: Keith Packard <keithp@keithp.com>
Add serial driver support for Renesas RZ/G3E
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Initial SAU UART driver support for Renesas RA0 series
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Some MAX32 targets may fail to raise TX half/almost empty interrupts,
so add an optional workaround for those scenarios to ensure no missed
TX completion when using the interrupt API.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
In cc13xx_cc26xx, the TX interrupt seems to be generated once initially on
enable and subsequently, when buffer goes from full to empty (since we are
operating in 1-byte buffer mode).
Due to this, if the TX interrupt is cleared in the configure function, a
new TX interrupt will not be generated untill we transition from a full to
empty buffer, even though the buffer itself is empty.
When using Zephyr Interrupt-driven UART API, one first needs to enable TX
interrupts `uart_irq_tx_enable()`, and then write data from the interrupt
callback, after checking `uart_irq_tx_ready()`. In case of cc13xx_cc26xx,
calling `uart_irq_tx_enable()` unmasks the TX interrupt, however, it will
not generate a new TX interrupt. Thus the callback will not be called
unless we first write something to the uart (using polling-API), causing a
transition in buffer state.
According to TI docs, writing 1 byte to the buffer will also clear the
TX interrupt, so it does not make sense to try clearing the interrupt
manulally in `configure` function.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Refactor MAX32 UART driver to use pm_device_driver_init so that the
device is moved to the appropriate power state expected by the system
during initialization.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add PM policy constraints so that UART driver can prevent the system
going to sleep before all characters are sent or received.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Several NXP drivers require clock control subsystem name definition in
Devicetree. It prevents usage of clock control without subsystem such
as fixed-clock. fixed-clock can be used for early SoC enablement when
complete clock controller is not available or not required.
Allow optional usage of clock control without subsystem by using 0 as
subsystem name if the name is not defined in devicetree. Add the option
for port, i2c, spi and serial drivers.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Changes added to make g1 driver to be used across multiple
SoC's and also avoids use of multiple SOC symbols in the
source file for selecting between the similar but differently
named macros and reg definitions across multiple DFP's.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
