Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Add basic support for the Aesc Silicon GPIO controller.
This IP core has internal tri-states and therefore a read,
write and direction registers. Additionally, it has advanced
monitoring capabilities for interrupt generation; low or
high leve and rising or falling edge.
Interrupt support will be added later when ElemRV supports
interrupt in Zephyr.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add condition to check whether the pin is set as output before
reading the output high or low for gpio driver of Renesas RZ
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
support gpio wake up function.
change init stage from POST_KERNEL to PRE_KERNEL_1
because uart wrap init need to use the gpio functions.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
This macro doesn't accept a delay parameter anymore (well, it does, but
it's deprecated and will trigger build warnings). Just remove it from the
places that were still passing it.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
ASAN reports error with native_sim after "gpio info <TAB>":
runtime error: index 1 out of bounds for type 'gpio_ctrl [1]'
So, although the dev pointer was not used, don't even read it
from out-of-bounds of gpio_list.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
On certain platforms I2C is not enabled by default, causing build error.
Change pca_series driver to select I2C.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The reset function is originally designed to have no return value. If
the GPIO toggle fails, there's no indication for failure until I2C
transaction fails. Account for this by adding return value to the reset
function.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
add support for pca9538, pcal9539.
Add support for pcal6408 and pcal6416, which is originally supported
by pcal64xxa driver. These device has the same register layout as
pcal9538 and pcal9539 respectively, which means they can be seamlessly
supported by pca_series driver.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
This commit updates the function to only set output-related flags
(GPIO_OUTPUT_INIT_HIGH, GPIO_OUTPUT_INIT_LOW) when the pin
is actually configured as output. For input pins, only GPIO_INPUT and
other relevant flags are set.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
The SIUL2 external interrupt driver is a native implementation usable
across all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow
clean reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 GPIO driver is a native implementation usable across all
NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Enable the pin configuration as single-ended pull-up output, allowing for
a currentless, signal-only output.
Signed-off-by: Paulo Santos <pauloroberto.santos@edge.ufal.br>
The fast wake feature in the MSPM0 GPIO peripheral allows the GPIO module
to stay in a low-power state and detect interrupt events on the device pins
without requiring a high-speed clock. This allows the device to support
fast wakeup from low-power modes, such as STOP and STANDBY, on any GPIO
pin.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
EM4 wakeup interrupts are dedicated interrupts tied to specific
pins that enable wakeup from EM4 through reset. Add support
for using these interrupts instead of the regular interrupts when
the GPIO_INT_TRIG_WAKE flag is set.
Since it's not possible to tell what pin is associated with what
EM4WU interrupt at runtime, the driver must store a mapping table
sourced from device tree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
GPIO interrupts do not work on MCXA, MCXA has ICR register but feature
FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT value is 0, can't only use
this feature to support ICR. So adjust feature judgment.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
There will be an compilation error if there is no interrupt GPIO defined
in the device tree file, as parts of the config and data structs
have #if that depends on the presence of interrupt GPIO.
Use the same #if constructs also on the functions that use those
structs.
Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Remove the configs that are not actually used for anything anymore or
never were, or that are redundant with other configs, and don't have any
code changes outside of Kconfig to remove.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added the gpio driver for EFR series 2 devices.
The SILABS_SISDK_GPIO symbol is added to enable
support for the new GPIO driver.
The SOC_GECKO_GPIO symbol is retained for now to
maintain compatibility with existing drivers and
will be removed in a subsequent commit.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add support for special GPIOTE0 instance on nrf54h20/cpurad.
This instance requires special handling because:
- there is no support for PORT event (level interrupts)
- TE channels are fixed to the pin
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The GPIO block instance is based on the instance number during the
device driver initialization. This is not correct as instance numbers
in now way reflect any numbering scheme. Therefore, a DTS property
is introduced so that the block instance numbering is indicated
explicitly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
LUT sizes directly reflects the global data when enabled in dts
(even if no or few pins are really consumed). Also the PINCM
numbering across the series (g, l and c) is within 255, so fix
to use uint8_t to save the global space.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
All the HAL API/wrapper depends on PINCM indexing, which cannot
be derived from neither pin number nor the address offset.
With current approach, update the LUT table of possible PINCM's
for L series with GPIO A, B and C banks.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This change introduces GPIO_RX_PORT_IRQ_DECL() and GPIO_RX_PORT_IRQ_ELEM()
macros to conditionally generate GPIO port IRQ declarations and elements
only when the 'port_irq_names' property exists in the device tree node.
This improves code clarity and avoids generating unused code for ports
that do not have IRQ support for Renesas RX
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Reading back the raw interrupt status from the gpio controller, provides
the interrupt mask _without_ the controller's masking registers applied.
This means that e.g. a rising edge would trigger an interrupt even on
pins that are configured for falling edge only.
Fix this by reading the "enabled" interrupt status instead of the raw
one.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
The polarity mapping was swapped such that GPIO_INT_TRIG_LOW would
translate to high, and vice versa, on the chip configuration.
Swap the polarity to fix this.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
This commit implements the gpio_get_config handle for the gpio_mspm0
driver.
NOTE: Currently only handles input/output state and not configured flags
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
Prior to this commit, writing a gpio port would completely clear
the state of given port. This commit ensures that state is kept
when writing, reading and configuring gpio ports.
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
It is not possible to build anymore in that mode, so we do not
need to support it in this driver cmake files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
