Added the gpio driver for EFR series 2 devices.
The SILABS_SISDK_GPIO symbol is added to enable
support for the new GPIO driver.
The SOC_GECKO_GPIO symbol is retained for now to
maintain compatibility with existing drivers and
will be removed in a subsequent commit.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add support for special GPIOTE0 instance on nrf54h20/cpurad.
This instance requires special handling because:
- there is no support for PORT event (level interrupts)
- TE channels are fixed to the pin
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The GPIO block instance is based on the instance number during the
device driver initialization. This is not correct as instance numbers
in now way reflect any numbering scheme. Therefore, a DTS property
is introduced so that the block instance numbering is indicated
explicitly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
LUT sizes directly reflects the global data when enabled in dts
(even if no or few pins are really consumed). Also the PINCM
numbering across the series (g, l and c) is within 255, so fix
to use uint8_t to save the global space.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
All the HAL API/wrapper depends on PINCM indexing, which cannot
be derived from neither pin number nor the address offset.
With current approach, update the LUT table of possible PINCM's
for L series with GPIO A, B and C banks.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This change introduces GPIO_RX_PORT_IRQ_DECL() and GPIO_RX_PORT_IRQ_ELEM()
macros to conditionally generate GPIO port IRQ declarations and elements
only when the 'port_irq_names' property exists in the device tree node.
This improves code clarity and avoids generating unused code for ports
that do not have IRQ support for Renesas RX
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Reading back the raw interrupt status from the gpio controller, provides
the interrupt mask _without_ the controller's masking registers applied.
This means that e.g. a rising edge would trigger an interrupt even on
pins that are configured for falling edge only.
Fix this by reading the "enabled" interrupt status instead of the raw
one.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
The polarity mapping was swapped such that GPIO_INT_TRIG_LOW would
translate to high, and vice versa, on the chip configuration.
Swap the polarity to fix this.
Signed-off-by: Emil Dahl Juhl <emdj@bang-olufsen.dk>
This commit implements the gpio_get_config handle for the gpio_mspm0
driver.
NOTE: Currently only handles input/output state and not configured flags
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
Prior to this commit, writing a gpio port would completely clear
the state of given port. This commit ensures that state is kept
when writing, reading and configuring gpio ports.
Signed-off-by: Hans Binderup <habi@bang-olufsen.dk>
It is not possible to build anymore in that mode, so we do not
need to support it in this driver cmake files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Replaces binary literal with 3ULL to avoid shift overflow and align
with Zephyr coding style.
Fixes: #81963
Fixes: CID 434591
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
The usage of nrf_gpio_port_retain_disable/_enable, in cases where
the soc pins support retention, every pin must be
retained/unretained regardless of what power domain the pad is in.
This patch ensures retain is applied to all pins in all domains by
the gpio_nrfx device driver, not only pins specifically in the
fast_active_1 domain. Without this patch, pinctrl will correctly
retain pins, while gpio_nrfx will fail to unretain them when
again.
We no longer check the output state either, which was passed with
the flags arg of gpio_nrfx_gpd_retain_set() so this arg has been
removed.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The WCH GPIO peripheral integrates with the EXTI and supports firing
interrupts when a GPIO pin changes.
Add optional support for firing a callback on rising edge, falling
edge, or both edges.
Tested on the `linkw` and the `ch32v006evt` using
`samples/basic/button`.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RA8P1 has 14 ports (from 0 to d) and 32 external irq while current
driver support 12 ports (0 to b) and 16 external irq.
This add addtional support for remain ports and external irq to be
able to work with RA8P1.
Fix the lack condition GPIO_RA_IOPORT for GPIO_RA_HAS_VBTICTLR
config
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
For the negative errno rzt2m_gpio_get_pin_irq may return to be properly
handled, irq variable needs to use signed type.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Coverity is reporting a possible untrusted loop bound, caused by accessing
num_pins through a tainted pointer. Use explicit type cast to keep coverity
happy.
CID: 347195
Signed-off-by: Loic Domaigne <tech@domaigne.com>
Fix an issue where calling gpio_pin_interrupt_configure
with edge mode and later calling it with level mode, did
not release the allocated gpiote channel.
Repeating the above sequence caused us to run out of
gpiote channels.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Add support for nPM1304 in the npm13xx drivers. The nPM1304 supports
different voltage and current ranges which are handled through the
initialization macros.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Rename npm1300 to npm13xx in function names, documentation, etc. where
applicable for all the npm13xx drivers
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Rename npm1300 drivers and header files to npm13xx to allow for usage
with other nPM13xx product variants.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Use signed variable for negative error codes so that potential errors
are actually detected and returned properly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
If supported, the data and control source for a signal can come from
either software or hardware. This change adds a custom configuration
flag to set this for a specific pin.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
- Adding support for GPIO_DISCONNECTED mode.
- Removing redundant interrupt configuration logic from the
.pin_configure API (already handled in pin_interrupt_configure).
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Remove gpio clock management from the GPIO driver when running on the
cortex-m33 on the mp2 and gpio clocks are managed by the cortex-A, being
the resource manager, allowed by the Resource Isolation Framework (RIF).
Also add a specific binding for the mp2 gpio to make clock property
optional.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Implement conditional compilation to avoid the warning:
- Use LL_PWR_EnableVDDIO2() for STM32U3 series.
- Use LL_PWR_EnableVddIO2() for other series.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
gpio_rpi_isr() always addressed io_bank0->proc0_irq_ctrl, so any
interrupts taken while code was running on core 1 were invisible and
left pending.
Use get_core_num() to pick proc1_irq_ctrl when the ISR executes on core
1, ensuring callbacks fire from both cores.
Also fix stray `iobank0_hw` symbol for the correct `io_bank0_hw`.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
