Several MAX14906/916/915 SPI write paths ignore MAX149xx_REG_WRITE()
return values and proceed silently after SPI write failures.
Fixed by propagating SPI write errors in the affected paths.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
Several MAX14906/916/915 Read/ReadModifyWrite update paths use
MAX149xx_REG_READ() return values directly without validating SPI read
errors first. This leaves SPI read errors unnoticed and corrupts registers
by writing return values unconditionally.
Fixed by early returning on SPI read errors.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
When max149x6_reg_transceive is called with rw=WRITE and rx_diag_buff=NULL,
the SPI diagnostic response byte is returned instead of 0, even though the
write was proper and successful.
Fixed by restricting the offending branch to READ only.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
Extend the ESP32 GPIO driver to support ESP32-C5 by adding the
SoC series to the register struct compatibility defines.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable the interrupt before reconfiguring its type to prevent
spurious triggers and edge detector asymmetry. Without this, the
first gpio_pin_interrupt_configure(GPIO_INT_EDGE_BOTH) can leave
the edge detector in an inconsistent state causing a persistent
timing offset between rising and falling edge detection.
Also skip the enable call when the requested mode is disable,
avoiding a redundant enable immediately after setting the type to
GPIO_INTR_DISABLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ISR bits are set on input level or edge changes, regardless of whether an
interrupt is actually enabled on that line. Therefore, we check whether an
interrupt is actually enabled by masking with IMR. If we didn't do this,
some other enabled interrupt firing could also result in a callback for a
disabled interrupt.
Signed-off-by: Bert Abrath <bert.abrath@basalte.be>
The RX GPIO was originally develop for RX130 MCU which only have port
0 to 5 and A to J, this commit add missing port initialize for other RX
MCU family
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Apply PINCTRL_STATE_SLEEP on suspend and PINCTRL_STATE_DEFAULT on resume
to ensure pins take on the DTS defined sleep state if one is defined.
TURN_ON already applies PINCTRL_STATE_DEFAULT (could be removed
potentially). RESUME handles the case where the device suspends without
full power-off.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
For Cortex-A Core, Zephyr runs on non-secure world, the bit in PCNS
or ICNS for corresponding GPIO pin is 1, no need to clear it and
Cortex-A Core could access the corresponding pin's regitsters, so
disable this feature for Cortex-A Core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The pcf857x_port_set_raw() function has a race condition where
the lock is only taken after the I2C write to update the cached
outputs_state. This allows concurrent threads to read stale
outputs_state values and compute tx_buf based on outdated data.
Since PCF8574/PCF8575 devices have a single output register that
is written atomically (all pins at once), a stale read causes one
thread's pin changes to be overwritten by another thread's write.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
The `gpio_stm32_configure()` function is used by both the GPIO and PINCTRL
drivers to configure I/O pins. Move it to the GPIO port manager module's
code so it can be shared properly and update both drivers accordingly.
With this change, the GPIO and PINCTRL drivers are completely decoupled.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On STM32 hardware, the GPIO port's MMIO interface is used for two purposes
which have their own separate Zephyr API: controlling the state of digital
I/O pins directly (GPIO API) and configuring I/O pins for a specific usage
(PINCTRL API). Historically, this was handled by having the PINCTRL driver
call inside the GPIO driver which works but creates a dependency loop.
Introduce a new `GPIO port manager` module in SoC-specific common code that
takes over various from the existing GPIO/PINCTRL drivers: GPIO port device
instantiation and `GPIO port index -> device` mapping respectively.
Modify the GPIO and PINCTRL drivers to make use of this GPIO port manager
module - a first step in decoupling both drivers from each other.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the helper function which computes the LL pin value from a pin number
to the <stm32_gpio_shared.h> header as this function can be useful for
modules other than the GPIO driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the ports list from the GPIO driver to a shared SoC-specific header.
This will allow reuse from other drivers such as pinctrl.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The function is only used from the device's PM action and is very trivial.
Inline it inside gpio_stm32_pm_action to simplify the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The STM32 pinctrl dt-bindings headers were full of definitions used by the
SoC-specific pinctrl header (<pinctrl_soc.h>) rather than from Devicetree.
Move these definitions to the appropriate header. While at it, include the
<pinctrl_soc.h> header from GPIO driver instead of series-specific pinctrl
header since it uses these definitions.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a GPIO driver for the Infineon CYW43439 WiFi chip that exposes
WL_GPIO0-2 as standard Zephyr GPIO pins. Pin 0 is the onboard LED
on Raspberry Pi Pico W and Pico 2 W boards.
The GPIO node is a child of the AIROC WiFi device node in the
devicetree. GPIO control is performed via the WHD gpioout iovar,
serialized with a mutex. A shadow register tracks pin state since
the CYW43439 does not support GPIO readback.
Signed-off-by: John Lin <mcjelcom@gmail.com>
Remove instance specific Kconfigs (CONFIG_NRFX_GPIOTEx) as they are no
longer used. Cleanup in all places.
Add prompt to CONFIG_NRFX_GPIOTE to allow enabling the driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If CONFIG_GPIO_NRFX_INTERRUPT is disabled then nrfx_gpiote driver API
shall no be accessed at all (driver can be disabled).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Infineon PSOC4 parts share many ports with a single IRQ line. Using the
SHARED_INTERRUPT handler feature of Zephyr results in a very large IRQ
vector table. Instead structure in DT the idea that the ports are
sharing an interrupt with a sort of pseudo interrupt controller.
This also rectifies the need to ifdef on CAT1C/M0+. I added a note
making it clear that in those cases we likely need to rework the way
interrupts are done anyways as there's secondary interrupt
muxes/controllers involved.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
Use IF_ENABLED when possible to keep code indents looking nicer rather
than ifdef's. Rename everything to be ifx (drop the cat1 naming). Drops
the unused intc_prio config member.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
- Fix lp_gpio Kconfig dependency to use proper
DT_HAS_ESPRESSIF_ESP32_LPGPIO_ENABLED symbol instead of
SOC_ESP32C6_LPCORE, and separate GPIO_ESP32 from LPGPIO_ESP32
- fix lp_gpio compatible string to espressif,esp32-lpgpio to
match the corrected Kconfig dependency
- enable global LP core interrupts at startup via
ulp_lp_core_intr_enable() in lp_core_startup(); the LP core
has no interrupt allocator so this must be done once for any
peripheral using the single interrupt vector
- enable lp_gpio in gpio_wakeup sample overlay
- fix ESP_CONSOLE_UART_NUM default for LP HP UART console
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Enables GPIO input+output mode to enable gpio_api_1pin test
- Retains current pin state when no output init flag specified.
- Adds pull up register validation, sets pull up register in
both pull-up and pull-up+pull-down cases.
Signed-off-by: John Batch <john.batch@infineon.com>
Refactors the drive mode selection logic for input and output pins into
dedicated helper functions.
Signed-off-by: John Batch <john.batch@infineon.com>
Fix incorrect array index on line 101. Should use cfg_idx (which accounts
for non-contiguous pin layouts) instead of pin when accessing pin_muxes
array elements. This prevents potential out-of-bounds access and ensures
correct pull configuration on i.MX RT118x SOCs.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Update Renesas RA GPIO driver to support Renesas RA0 series
- Add macro to disable port external interrupt the the compatible
nodes `renesas,ra-external-interrupt` are not enabled.
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This was not noticed because there is currently no STM32 with a GPIOW port,
but adding it to the list is better for future-proofing.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On BL70x, pins 23-28 are output-only and must be routed through the
PSRAM IO pads. When PSRAM is not enabled, set GLB_GPIO_USE_PSRAM_IO
so these pins are usable as regular GPIOs.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Use BIT(pin) instead of the raw pin number when setting or clearing
GPIO output values. Without BIT(), only the lowest pins were
affected and higher pins were never toggled.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Enable CONFIG_SHARED_INTERRUPTS to allow multiple devices
to register handlers on the same IRQ line.
Replace irq_connect_dynamic() with IRQ_CONNECT() to configure
interrupts at build time, eliminating runtime setup overhead.
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
`gpio_xec_pin_interrupt_config` returned early when the computed IDET
configuration matched the current CR1 IDET field. On some reset paths
the GPIO control register can retain the same IDET value while the
interrupt aggregator state is reset/reconfigured. In that case, the
early return prevents re-enabling the aggregator and interrupts remain
disabled.
Remove the IDET equality early-return so the driver always updates the
level/edge bookkeeping and programs the interrupt aggregator enable
state.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
The GPIO ISR needs both a pointer to the device object and its data block
(because the callback linked list is stored in the data block). Sicne the
device object has a built-in pointer to the data block, using that as the
ISR's argument allows obtaining all we need "for free" whereas the current
approach wastes 4 bytes of RAM per GPIO port instance.
Note that once compiled, the reworked ISR is effectively identical to the
old one (only the offset of one `ldr Rt, [Rn, #off]` changes).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The drive mode validation added in commit ede19a4337 was rejecting
valid configurations for input pins. The validation ensures that
GPIO_SINGLE_ENDED and GPIO_LINE_OPEN_DRAIN flags match the hardware
capabilities of each MCP23xxx variant (push-pull vs open-drain).
However, this validation was applied to all pin configurations,
including input pins. Input pins do not have a drive mode, so
applications typically configure them without setting drive mode flags.
This caused the validation to incorrectly reject input pin configurations
with -ENOTSUP.
Fix by only validating drive mode flags when GPIO_OUTPUT is set.
Input pins now configure successfully, while output pins still receive
proper validation to ensure the requested drive mode matches the
hardware capabilities.
Fixes: ede19a4337 ("drivers: mcp23xxx: add support for open-drain ...")
Signed-off-by: Cliff Brake <cbrake@bec-systems.com>
When calling `gpio_pin_configure` with GPIO_OUTPUT_INIT_LOW or
GPIO_OUTPUT_INIT_HIGH, it is expected from the driver to set initial
output state. The current driver implementation does not set this
user provided initial state.
This commit sets requested output state before changing channel mode
to output.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
