Ensure gpio_set_dir() receives GPIO_IN or GPIO_OUT by mapping
INIT_{LOW,HIGH} flags explicitly, instead of passing raw bitmasks.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Fixed several occurrences of offset not being calculated in case
multiple GPIO ports are present.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
If gpio-reserved-ranges to reserve some pins which used by other CPU
Core's OS, we could only handle usable pins owned by current CPU
Core in interrupt handler.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
If the platform uses SCMI pinctrl driver, pinctrl regitster can't accessed
by CPU Core directly, and currently SCMI pinctrl driver has no API to read
back the register value, so use default pad config value for GPIO pad
configuration, and in theory we could use a fixed pad config value in this
driver as each new GPIO configuration has no relation with previous
configuration.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The gpio_smartbond driver incorrectly uses the static
PM_DEVICE_DEFINE() and PM_DEVICE_GET() macros when creating a driver
instance from a devicetree instance number.
Update to use PM_DEVICE_DT_INST_DEFINE() and
PM_DEVICE_DT_INST_GET() macros.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
If GPIO_INT_WAKEUP is in the trig argument, the selection
of trigger mode breaks because the GPIO_INT_WAKEUP flag
breaks the equal comparisons.
Signed-off-by: Mike J. Chen <mjchen@google.com>
This change would also solve that according to the C11 standard,
section 6.5, paragraph 4, the usage of bitwise operators on
signed integers is implementation defined.
Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
Currently, the Zephyr dt requires address to the direction register
instead of the base GPIO address. usually means base address + 0x10 when
compared with Linux.
To make things more consistent between linux and zephyr, handle the
direction offset in the driver itself. This also lays the foundation for
supporting more than 32 GPIOs per port in the future by introducing
offsets for all the banks.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Currently to set/clear the pins, we do a logical OR of the value with the
existing values in set/clear registers. However, reading these registers
always returns the value in out_data register. This is undesirable as it
can cause unnecessary complications. Consider the following scenario:
We need to set PIN 0:
set_data |= BIT(0)
We need to clear PIN 1:
clr_data |= BIT(1)
The latter would also clear the 0th bit due to the aforementioned
behaviour.
This patch fixes this by writing the mask directly without ORing.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
The current procedure to initialize the GPIO is:
If the GPIO is configured as GPIO_OUTPUT and also has the
GPIO_OUTPUT_INIT_HIGH flag, set it to output high; otherwise, set it to
output low.
This may fail if the GPIO is simply configured as GPIO_OUTPUT without
specifying either INIT_HIGH or INIT_LOW, which means it is intended to
preserve the previous status. But in this case, we are currently setting it
to output low.
Fix this by explicitly initializing the GPIO to high or low according to
the configuration:
If the GPIO is configured as GPIO_OUTPUT and also with the
GPIO_OUTPUT_INIT_HIGH flag, set it to output high.
If the GPIO is configured as GPIO_OUTPUT and also with the
GPIO_OUTPUT_INIT_LOW flag, set it to output low.
If the GPIO is configured as GPIO_OUTPUT only,
do not set the output value.
Signed-off-by: Benson Huang <benson7633769@gmail.com>
Add a GPIO driver support for TI MSPM0 SoC family.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
The pinctrl register bits need to be restored to GPIO mode
after we exit from certain low power modes. We cannot rely
on the pin function to default to GPIO.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Added the possibility of leaving the gpio-int property empty, in case
the corresponding pin is not connected.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Fix device initialisation, allowing for empty interrupt_gpios in the
dts, as suggested by the documentation.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Implement PM_DEVICE_RUNTIME for gpio_nrfx.c
PM is required to request/release the GPD domain if such exists
for a given GPIO instance. Without this, every single API call
will result in a requesting the GPD domain, which makes it slow
and unusable from ISRs, given GPD requires IPC. Now, user can
simply get the GPIO before using it, and put it once done,
calling the APIs from ISR while resumed.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Ignore error if default pinctrl missing. Some devices allow specifying
pinctrl in them, which is better to do , specially for static (on-board)
devices to keep overlays simpler.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Properly dereference the value pointer in assignment.
```
In function 'gpio_pca_series_port_read_standard':
warning: assignment to 'gpio_port_value_t *' {aka 'unsigned int *'} \
from 'uint32_t' {aka 'unsigned int'} makes pointer from integer \
without a cast [-Wint-conversion]
1071 | value = sys_le32_to_cpu(input_data);
| ^
```
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Move the direction reset to config init function. This ensures that regs
is read after the DEVICE_MMIO_NAMED_MAP is called, which is where the
init for RAM MMIO takes place
Tested on PocketBeagle 2 A53s.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
The nRF GPIO hardware does not store the initial output value
set resulting from gpio_pin_configure() and thus, when
gpio_get_config() is used, the initial value is not returned.
This commit just reads the output value and sets the INIT
value to match in gpio_get_config().
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Mass renaming is carried out to unify some prefixes and shorten some
macros, making the code easier to maintain and support new devices.
- Rename `int_dev` to `gpio_int_dev` for gpio interrupt
- Rename `eirq` to `ext_irq` for external interrupt
- Rename `gpio_rz_hw_config` to `gpio_rz_flags`
- Rename `p_pm` to `gpio_flags`
- Rename `pre_flags` to `rz_flags`
- Remove `_IOPORT` and `_PIN_CONFIGURE` in some macros
- Rename `GPIO_RZ_PIN_CONFIGURE_GET_FILTER`,
`GPIO_RZ_PIN_CONFIGURE_GET`, `GPIO_RZ_PIN_SPECIAL_FLAG_GET` to
`GPIO_RZ_FLAG_GET_FILTER`, `GPIO_RZ_FLAG_GET_CONFIG`,
`GPIO_RZ_FLAG_GET_SPECIFIC` respectively
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit adds a padding of 0x10 bytes at the beginning of the
`gpio_davinci_regs` structure to correctly align the register
definitions with the actual register layout.
Previously, the DTS had to manually offset the base address by
0x10, introducing a special case in Zephyr's Davinci GPIO driver.
This change eliminates the need for that workaround
Adding the paddingi also help to maintain a similarly with also
to the linux counterpart.
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
Change the base address of GPIO and pinctrl voltage selection
The new base address enables more pins to support voltage selection.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This driver was setting all GPIO lines to input and the data register to
zero on initialization. This does not appear to be common practice among
other GPIO drivers, and in fact caused a serious problem on the ZynqMP
platform, where between 1 and 4 of the top-most GPIO lines are
frequently used by platform firmware and Vivado as reset lines for the
programmable logic. Since these resets are active low, and their
input/output state is ignored due to how they are connected to the EMIO
GPIO outputs from the PS, this caused the PL reset to be asserted when
the GPIO driver initialized, preventing any logic using that reset from
functioning properly.
There may also be other cases where GPIO line states have already been
set by the boot loader or firmware and clearing them may result in
improper behavior or glitches on the lines during initialization.
Update the driver to disable GPIO interrupts but leave the pin
modes/states unchanged until/unless they are explicitly reconfigured.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The Kconfig help text for the SN74HC595 driver refers to the device
as a "GPIO extender", which is inconsistent with the devicetree
binding file (ti,sn74hc595.yaml) that describes it as a "GPIO expander".
Signed-off-by: Hank Wang <wanghanchi2000@gmail.com>
Initial commit for GPIO driver support on board using RX130 MCUs
* drivers: GPIO: implementation for GPIO driver on RSK_RX130_512KB
* dts: rx: add device node for GPIO of RSK_RX130_512KB
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Don't automatically disable all GPIO ports just because
`PM_DEVICE_RUNTIME` is enabled. Require the user to explicitly call
`pm_device_runtime_enable` on the port, or add
`zephyr,pm-device-runtime-auto` to the devicetree node.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The i.MXRT10xx series have configurable GPIO pull strengths.
These are available for configuration in the pinctrl system, but not for
regular GPIO use.
This commit adds SOC-series specific GPIO configuration bits for selecting
weak or strong GPIO pulls, similar to drive strengths available from other
GPIO pin configuration examples.
This has been tested on a custom i.MXRT1062 product.
Signed-off-by: Stefan Giroux <stefan.g@feniex.com>
Driver is using local macro to get current CPU ID and it is now
in conflict with generic CPU_ID. Added prefix to avoid conflict.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
