Preserve the volatile qualifier when casting the shared memory pointer
in flash_cpu01_receive_cb() to avoid dropping volatile semantics during
inter-processor communication.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Preserve original write length for DCACHE_InvalidateByRange()
Guard declaration of `size` with CONFIG_HAS_MCUX_CACHE to avoid
unused-variable warnings when cache is disabled
Add pointer validity checks before cache invalidation
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This modification prevents the bet pointer from being nulled at the end
of the loop, which would otherwise render the search for a suitable
erase type ineffective. It also optimize the loop as it omits
unnecessary operations.
Without this change, the erase size defaults to one sector. If the chip
defines fewer than JESD216_NUM_ERASE_TYPES (=4) erase types, this
behavior still works, as the resulting command will correspond to a
sector erase operation. However, if the chip defines all erase types,
the resulting command will be the one specified in the erase type. But
since bet is nulled, the erase size will incorrectly default to the
sector size.
Signed-off-by: Martin Gysel <me@bearsh.org>
Current driver protections prevent to initialize driver when run as from
an external application running from ext flash. Aim is to avoid performing
full driver initialization of the NOR flash controller the application
is read from.
But this problem is actually only valid when application is running in XIP
mode (read in memory mapped mode at run time).
In ram load mode, since there is no direct activity from the application
on the NOR device, nothing prevents the ext flash driver to be used fully.
Hence, we should allow the controller initialization to happen, with some
adjustments. Mostly, what we need is to:
- skip the hal init
- abort memory mapping afterwards to let the jedec reading happen.
Remove conditions around `stm32_xspi_is_memorymap()` and
`stm32_xspi_abort()` which can finally be useful in various cases.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This change removes the on-stack copying and instead
uses a pointer to the configuration to avoid unnecessary
stack usage
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
STM32H5 series now uses the dedicated `flash_stm32_xspi` driver instead.
Remove all quirks related to H5 in the STM32 OSPI driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Allow passing some context to the shell bypass callback function by
providing a void pointer user data argument.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add flash controller driver for the on-chip C40 flash controller
The driver is backed by the MCUX C40 HAL and implements
read/erase/program, page layout, and an optional protection policy
that can lock well-known regions (IVT/MCUboot) derived from devicetree.
Key details:
- Selects FLASH_HAS_DRIVER_ENABLED / FLASH_HAS_EXPLICIT_ERASE /
FLASH_HAS_PAGE_LAYOUT.
- Runs erase/program from SRAM when XIP by relocating both the shim and
the MCUX HAL source if CODE_DATA_RELOCATION_SRAM=y.
- Optional protection pass at init (FLASH_MCUX_C40_APPLY_PROTECTION),
which aligns windows to sector boundaries and applies lock/unlock
using the HAL. This is useful on XIP systems to keep IVT/bootloader
ranges read-only; can be disabled if a bootloader or security policy
manages protection instead.
Files:
- drivers/flash/flash_mcux_c40.c (new)
- drivers/flash/CMakeLists.txt (+zephyr_code_relocate when needed,
Compliance fixes)
- drivers/flash/Kconfig.mcux (enable flash driver, reloc & protection)
- modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
STM32H7 platforms now enable cache management by default.
To ensure data coherency after flash writes, invalidate cache
lines to the region written.
This prevents stale data and ensures proper memory visibility.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
add SOC_SERIES_STM32N6X dependency with USE_STM32_HAL_DMA_EX
to enable building applications that use XSPI with DMA
configuration.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
This is a follow-up to commit d1abe40fb0.
Function `qspi_wait_while_writing()` (and also `qspi_rdsr()` that is
called by it) is now always required for `qspi_erase()`, so it can no
longer be under `#if !IS_EQUAL(INST_0_QER, JESD216_DW15_QER_VAL_NONE)`.
Also definition of `dev_config` in `configure_chip()` needs to be moved,
as for QER set to NONE, it is not used and causes a compilation warning.
Add a test case that will ensure the driver can be built successfully
with `quad-enable-requirements = "NONE"`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Updates DMA includes from the modules needed for DMA PDL based driver
implementation.
Cleans up cmake to use only USE_INFINEON_DMA Kconfig option to select
dma files from PDL/HAL.
Signed-off-by: John Batch <john.batch@infineon.com>
Add bus idle wait after clock rate query to ensure AHB transactions
complete before device configuration. This prevents XSPI_SetDeviceConfig
from failing due to ongoing AHB access detection in XIP environments.
The issue occurs because clock_control_get_rate() triggers AHB
transactions that complete asynchronously, causings subsequent device
configuration to fail due to its bus status checking.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
The QSPI delayed data sampling (SSHIFT) is enabled by default. This
feature is configurable in both XSPI and OSPI drivers. Align with
these drivers and make the feature configurable for QSPI too.
Signed-off-by: Adam Zotow <azo@trackunit.com>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use the series-agnostic STM32 LL headers from the STM32Cube HAL module
instead of series-specific ones in STM32 drivers.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Improve erase efficiency by using a hybrid approach that combines block
and sector erase operations.
The new implementation:
- Erases unaligned sectors at the start until block-aligned
- Erases whole blocks in the middle protion
- Erases remaining sectors at the end.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The driver currently provides no way to use Dual IO Read and Single IO
for the rest of the commands currently, and would erroneously use
Single IO PP command in Dual IO mode. This PR fixes and adds
support for that.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Remove the Boolean tracking of MSPI IO mode as we can now rely on
tracking the entire dev config applied to the MSPI device, multiple
of which will exist in later commits.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Also in preparation for allowing control command frequency to be
different from the read/write frequency and initialization frequency.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Instead of just tracking in a bool whether the MSPI device is in
Standard MSPI vs. QPI/OPI config, track the entire MSPI config which was
last applied. This makes it easier later to track more than two configs
to apply based on the next command to transceive.
Signed-off-by: Utsav Munendra <utsavm@meta.com>
Flash MSPI NOR driver already has support for flash page layout, but did
not select the Kconfig symbol indicating so. Add the selection so
drivers can use the page layout api.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Fix typos in the driver instantiation macro, which leads to page_size
and timeout_erase defaulting to 0 regardless of whether the
devicetree instance has the read-only property or not.
DT_INST_NODE_PROP_OR() -> DT_INST_PROP_OR()
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
MCXW2XX ROMAPI provide the function FLASH_CacheClear to clear the cache.
The SMSCM is not supported on MCXW2XX platform.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the READ_BIT macro (defined in
the STM32 HAL) by stm32_reg_read_bits.
Fixes some cases where the return value was tested like a boolean
despite not being one.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Initial support Flash-LP driver for Renesas RA
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
The Kconfig symbols for selecting HAL content should be part
of the HAL module integration, not defined by the SoC. Split the
symbols between the Series 0/1 Gecko HAL and Series 2 SiSDK HAL
when moving them.
For now, the Series 0/1 HAL symbols retain their name, while new
names consistent with the symbols already defined in the module
integration layer are used for the Series 2 HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This driver is based on the XSPI driver for Renesas RZ/T2M and N2L,
and the SPIBSC driver for Renesas RZ/A3UL from the HAL.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Direct flash access can cause exceptions when performed while the flash
memory is inaccessible or being modified — for example, when code is
executing from PSRAM. To avoid such invalid access, this change introduces
asynchronous flash operations that are executed from a safe runtime context
via a work queue. This ensures all flash accesses occur only when the flash
is valid and accessible.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The STM32 QSPI, OSPI, and XSPI drivers support sending the ULBPR command
for flash ICs that require unlocking before writing to. This is done
conditionally based on the requires_ulbpr devicetree property.
Previously the driver would always log "Write Un-protected", even if a
write un-protect was not attempted. Fix this so that "Write Un-protected"
is only logged when a write un-protect is attempted and succeeds.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Extend the IT51XXX M1K flash controller driver to implement the flash
extended operation (ex_op) API. This allows runtime selection of both
the flash device and the addressing mode:
Flash target selection:
- FLASH_IT51XXX_INTERNAL: on-chip SPI eFlash
- FLASH_IT51XXX_EXTERNAL_FSPI_CS0: external SPI flash on FSCE0#
- FLASH_IT51XXX_EXTERNAL_FSPI_CS1: external SPI flash on FSCE1#
Addressing mode selection:
- FLASH_IT51XXX_ADDR_3B: 3-byte (24-bit) addressing mode, supports
flash devices up to 16MB capacity
- FLASH_IT51XXX_ADDR_4B: 4-byte (32-bit) addressing mode, required
for devices larger than 16MB
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
