Add a guard clause in flash_esp32_read() to return 0 when the
requested length is zero. This avoids unnecessary operations
and aligns with expected flash API behavior, where reading
zero bytes is treated as a no-op.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a workaround for `NRF53_ERRATA_159_ENABLE_WORKAROUND`
instead of simply printing an error and failing the transaction.
Signed-off-by: Anthony Williams <anthony289478@gmail.com>
For devices other than the stm32h745/747/755/757 that use
dual-core cortex-M4/cortex-M7, do not multiply flash
controller size by 2. Single-core stm32h7x devices define
their flash-controllers dtsi as a single area, not two banks.
Use the presence of the bank2-flash-size prop to determine if
this is a dual-core stm3h7x or not.
Signed-off-by: Rory Piper <rory.piper@signal-fire.com>
This commit adds support for the new cs-high-time devicetree property.
The QUADSPI_DCR_CSHT is now configured according to the value indicated
in the devicetree, for both single and dual flash modes.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
The QSPI 1/2 sample shift (SSHIFT) was only enabled in dual flash mode.
This feature is useful to guarantee that data is ready at the sampling
moment, even if the signals are a bit delayed due to PCB constraints.
Therefore, it should be enabled when possible (only supported in STR
mode).
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Remove these legacy kconfig, not necessary.
The DT already has the bindings and nodes required to represent if there
is a FlexSPI and/or SEMC.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds JEDEC-ID check to the flash_mcux_flexspi driver
if it is defined in DTS.
- Avoids applying DTS settings to a different flash module.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add the extended operations to the Andes XIP flash driver.
The extended operations supports:
- reading status registers of the flash chip
- changing status registers of the flash chip
- software lock of the status registers
- modifying SPI read command used in memory-mapped mode
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The flash M1K driver supports read (up to 1K), write (1K), and
erase (4K) operations, which can be accessed via DLM.
Accessible flash regions include internal e-Flash or external SPI
flash via FSCE# or FSCE1#.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
- Adds CONFIG_FLASH_PAGE_LAYOUT check to the flash_mcux_flexspi
drivers.
- Saves some memory if FLASH_PAGE_LAYOUT is disabled.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Remove cache invalidation after flash write,
cpu should automatically invalidate cache but
for HW erase invalidation needed due to erase
from different bus.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Although the value currently hard-coded in the driver (10 ms) is quite
high, it may turn out to be insufficient when there is a need to use
some very low SCK frequency, like 250 kHz.
Make the timeout value configurable per-instance, via devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Cleaned up the flash_rpi_pico driver to improve code readability and
compliance with Zephyr coding standards. Fixed inconsistent indentation
across the file and removed variables that were declared but not used.
A few improvements are credited to Manu3l0us.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
The Raspberry Pi Pico 2 uses a QMI flash controller, which differs from the
SSI controller used in the original Pico. Zephyr already has support for
the SSI controller, but lacked support for QMI.
This change adds the QMI flash controller implementation in the
flash_rpi_pico.c driver file. Additionally, the RP2350 SoC devicetree file
(rp2350.dtsi) has been updated to enable and describe the flash controller
for Pico 2.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
Use wrapper function for read operations to allow using the new HAL
function that handles ECC checks and erased page detection.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
To fix MAX32690 flash problems, I created a wrap version of
MXC_FLC_Write(...) function which disables ICC before calling write
function and enables ICC after this function.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Disable interrupts during flash operations to prevent unintended jumps.
Interrupts are now disabled before read, erase, and write operations to
avoid accidental jumps to other flash sections while working on a
specific section.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
When dual-flash mode is enabled, any erase operation is executed on both
flash memories in parallel. This means from the flash driver's point of
view, the size of a given sector/block is twice the size of a
sector/block on a single flash memory.
For example, assuming 4-KiB sectors for each flash memory, if the flash
driver is asked to erase at address 0x0000, the erase size must be a
multiple of 8 KiB since each sector erase operation will cause a 4-KiB
sector to erased in each flash memory.
Before this commit, the doubled erase size was only considered in
'setup_pages_layout'. Now, the actual sizes of the erase operations are
properly set in the flash driver's data and are used everywhere in the
driver.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
When dual-flash mode is enabled, even bytes are written to the first
flash memory and odd bytes to the second flash memory. This means, from
the flash driver's point of view, the size of a flash page is twice the
size of a single flash memory's page.
So if each flash memory has 256-byte pages, 512 bytes should be used as
page size by the flash driver. Using 256 bytes was working fine but is
suboptimal.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
When dual-flash mode is enabled, two identical flash memories are
connected to the QUADSPI peripheral, each having its own set of
registers. This means that when reading or writing a flash register,
this has to be made for both flash memories.
For example, when reading a status register (1 byte), the QUADSPI
peripheral must be configured to read two bytes of data, which
correspond respectively to the value of the register in the first and
second flash memory. Same thing when writing.
Before this commit, when dual-flash mode was enabled, only the register
of the first flash memory was considered, which means the second flash
memory could be incorrectly configured and that any write/erase
operation could be considered as completed too early, if the operation
takes more time to complete for the second flash memory.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
The 'qspi_read_status_register' routine implements the reading of a
flash memory's status register. This routine is used anytime reading a
status register is needed, except in 'qspi_wait_until_ready'. This
commit moves the read routine to be able to use it in
'qspi_wait_until_ready'. The 'qspi_write_status_register' is also moved
to keep it close to the read routine.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
In multiple places, "#if DT_PROP(DT_NODELABEL(quadspi), dual_flash) &&
defined(QUADSPI_CR_DFM)" was used to guard sections specific to
the dual-flash feature. This is quite long and "#ifdef
STM32_QSPI_DOUBLE_FLASH" is now used instead.
Note the presence of QUADSPI_CR_DFM is no more checked. This is not
considered as an issue since when QUADSPI_CR_DFM is not available, the
QSPI hardware doesn't support dual-flash mode so this mode must not be
enabled in the devicetree. With that change, enabling dual-flash mode
when not available causes a compile-time error.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Add a flash driver that is used to perform flash operations on a flash
chip that is connected to an Andes QSPI controller and is used for XIP
mode.
The driver is as small as possible, because necessary code has to be
placed in RAM. It is not possible to fetch code from flash while
performing erase/write operations.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a new flash for toggling runtime SFDP data fetching, and use static
devicetree properties by default. Clean up various minor items from review.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Properly configure the MAX32 SPIXF peripheral to use the SPIXF controller
for transparent memory mapped reads, and enable the SPIXF main controller
and use it for writes.
Add support for testing XIP support to the nocopy sample, which requires
flashing with OpenOCD with MAX32690 QSPI flash support.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The flash_stm32_xspi driver should not initialize the xspi,
if this one is being use to execute in Place : the init is skipped.
This mode is identified with the CONFIG_STM32_APP_IN_EXT_FLASH.
Checking the memory mapped mode bit is possible when the xspi
peripheral clock is not off (stm32h5 has no clock_control_get_status API)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
It is not possible to build anymore in that mode, so we do not
need to support it in this driver cmake files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The reset commands were sent only in SPI mode, causing the device not to
be properly reset when in QPI mode. On the STM32H747I-DISCO boards, this
was causing the driver initialization to fail due to a bad SFDP magic
after flashing the external memory using STM32CubeProgrammer since the
external loader is configuring the flash memory in QPI mode.
The commands are sent in QPI mode first, then in SPI mode:
- If the flash memory was in QPI mode, the two first reset commands are
processed and after reset, the flash memory is in SPI mode and
correctly handles the SPI mode reset commands.
- If the flash memory was in SPI mode, for each QPI command the chip
select signal will be released before the flash memory had the
opportunity to receive a whole command (1 byte), so the partially
received commands will be ignored and won't cause any harm. Then, the
chip is reset by the commands sent in SPI mode.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
When the QSPI is used in dual flash mode, e.g. on the STM32H747I-DISCO
board, only the first flash memory was reset and configured in 4-byte
addressing mode. This was in particular causing data to be incorrectly
read from the second flash memory and only even bytes were valid during
a read.
The dual flash mode was only enabled after reading the SFDP table since
it is desired to read the table of only one flash memory, not both.
This commit changes the driver to only disable the dual mode temporarily
while reading the SFDP table, ensuring all other commands and in
particular configuration commands are sent to both flash memories.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
MT35 flashes could run in octal mode, Now the driver doesn't support
octal mode, add octal mode support for MT35 flashes.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Use LOG_ERR() instead of LOG_DBG() in flash_fill() when this function
fails to perform the write operation, so that the failure is better
visible and its cause is easier to identify.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The STM32WBA Flash Manager driver is failing to erase a sector, instead of
erasing one sector, two sectors are erased.
Fix it by correctly calculating the number of sectors to erase
Signed-off-by: Eric Mechin <eric.mechin@st.com>
This commit changes the implementation to distinguish between is25lpXXX
and is25lpXXXd. Using RDERP as in the original solution didn't work for
is25wpXXX chips and would cause a halt. This new implementation reads
the AutoBoot register instead, which is not present in is25lpXXX but
present in is25lpXXXd, is25wpXXX and is25wpXXXd.
Tested on:
- mimxrt1020-evk
- mimxrt1170-evk rev. A
- custom board with mimxrt1170 and is25lp128d
Signed-off-by: John Barbero Unenge <git@lsrkttn.com>
New property of the st,stm32-qspi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-qspi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
New property of the st,stm32-ospi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-ospi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When the quad-enable-requirements property is set to "NONE" or is not
present, no Quad Enable operation should be performed.
This fixes an issue with the mx25uw6345g flash chip that is present
on the nRF54h20 DK and supports the Single I/O mode, but cannot be
used in that mode.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix timeout error that can occur in rare case.
When the thread writing to flash is pre-emptive it can be scheduled
out after reading the status register, but before checking if timeout
has expired. In this case it will report timeout without re-checking
the status register.
When writing a lot to flash, for example a firmware update process
then this situation is very likely to occur.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Some external flash modules have extra commands to support, for example,
reading/writing an OTP zone. Given that the commands are highly specific
and difficult to generalize, we add two ex ops that can be used to
transmit a custom command (in the form of a full QSPI_CommandTypeDef) and
then read or write a user-provided buffer.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
