Commit 857e5793f1 fix
the flash_mcux_flexspi_nor.c driver to wait for the
FlexSPI to be idle before performing write/erase
operations. Add a similar check to these drivers that
also use the FlexSPI NOR block.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add a simple non-XIP transaction before deactivating the QSPI after
a XIP transaction is performed. This prevents a CPU hang from occuring
when another XIP transaction is attempted after the QSPI is activated
again.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use cache API for disabling and enabling ICACHE. The driver handles waiting
for ongoing cache invalidation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Move MSPI NOR commands to rodata.
Replace array with empty padding (~1kB) with macro-based assignments.
Ref: NCSDK-32779
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Extend driver to support single lane and 1-4-4 IO modes.
Move flash chip quirks to a separate file.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Based-on-patch-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
-The stm32wba6x has Dual Bank memory. Change the flash driver
to support this OPTion given by presence of the
DUAL_BANK bit (21) in the FLASH_OPTR register.
-Flash erase with 2 banks: Add the control of the BKER
bit of the FLASH_NSCR1 to select BANK1 or 2 of
the internal flash depending
on the page number >127 for BANK2
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The LL_GetFlashSize function has been removed for
this new HAL H7RS release. Retrieves the value now from
the devicetree using the DT_REG_SIZE macro.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
IS25LPXXXD uses the same jedec-id as IS25LPXXX, but the latter has
an extended read register, similar to IS25WPXXX. This change will
attempt to read the extended read register to determine what the
appropriate initialization value for read register should be.
Signed-off-by: John Barbero Unenge <git@lsrkttn.com>
This commit adds the possibility to add additional custom
context for flash operations for usage by non-standard
flash drivers.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The implementation for erasing pages in the flash_sam.c driver
indicated a successful erase after exceeding the last page to be
erased successfully. Since the last page has no proceeding page,
the succeeded status was not set.
This fix switches around the status to be set as succeeded before
erase begins, to have the succeeded status cleared if page unlock
or erase fails.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add low-power-write property to MSC device tree node, set
MSC_WRITECTRL_LPWRITE if enabled.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Introduce separate flash driver for Silabs Series 2. This driver
is forked from the Gecko flash driver with no changes outside of
formatting and naming.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a flash driver intended to handle various flash devices
connected over MSPI bus as long as they support JEDEC SFDP.
This is an initial commit providing only basic operations
in Octal I/O mode with some hard-coded values for Macronix
MX25Ux series chips.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Looks like 9d5ebb3cbc introduced a new warning when building with
runtime sfdp on 32 bit platforms. Fix it for good by just casting the
operation to int and go back to use %u.
Tested with:
west build -p -b gd32f450z_eval samples/drivers/flash_shell \
-DCONFIG_SPI_NOR_SFDP_RUNTIME=y
west build -p -b mpfs_icicle/polarfire/u54 samples/drivers/flash_shell
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix few printf format warnings when building for
mpfs_icicle/polarfire/e51. PRIdPTR for the pointer difference, %zu for
size_t.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Adding k_usleep while polling the flash's busy status yields the CPU
resource, giving lower-priority threads the opportunity to run.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Fix flash read operation to account for all unaligned
scenarios, i.e, address, buffer and length. This is needed
when using flash APIs provided in ROM.
This also removes the unaligned flash write call as it
expects aligned values only.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Some flash devices enable entering the 4-byte address mode
by setting BIT(7) in a special register via a write instruction 0x17.
The support for this method is indicated in BIT(3) of
Enter 4-Byte Addressing byte in 16th DWORD of the JEDEC Basic
Flash Parameter Table.
Infineon's S25FL512S is an example flash device with this feature.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
There were some compilation errors caused by unused functions.
Add proper #ifdef statements not to include unused functions.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The BLE acronym is not an official description of Bluetooth
LE, and the Bluetooth SIG only ever refers to it as Bluetooth
Low Energy or Bluetooth LE, so Zephyr should as well.
This commit does not change any board or vendor specific
documentation, and the term BLE may still be used in those.
It will be up to the vendors to update it if they want,
since many of them are using the term BLE in their
products.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The Max flash size of the stm32H5 serie depends on the mcu device
from 256 to 1024 KB, in two banks.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename *write_protection functions to *cr_lock, because it is not
enabling real write protection. It only blocks changing register
by software accidentally.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Building with clang warns:
drivers/flash/spi_nor.c:306:20: error: unused function
'delay_until_exit_dpd_ok' [-Werror,-Wunused-function]
static inline void delay_until_exit_dpd_ok(const struct device *const dev)
^
delay_until_exit_dpd_ok is only used when ANY_INST_HAS_DPD is defined.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
XIP may indicate that the program is executed either in local memory
or flash. However, the SPI node is only used as a flash fetch device
when the program is executed in flash.
Therefore, optimize the related checks to ensure that when XIP is
enabled but the program is executed in local memory, the qspi flash
node can still be used.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
ATCSPI hardware limits single transfer to 512 bytes, so when reading
data over 512 bytes, it needs to be split into multiple transfers
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Move the memory barrier to a function that commits option bytes.
This way the barrier doesn't have to be added before every call of the
commit_optb function.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Change the return value of the write_opt function. If returns 0 if a
change of option bytes was not needed.
It gives callers of the function an information a commit of the option
bytes is needed.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The erase time varies between different SPI NOR flash chips.
Some have typical erase times in the 20-25ms range, at which point the
default 50ms poll interval means we get half the possible erase speed.
With slower memory, or larger erases, 50ms might not be a lot, but for
block erases, if we are unlucky we may end up polling just as the it's
about to finish erasing, and have to wait another poll interval.
Signed-off-by: Kamil Krzyzanowski <kamnxt@kamnxt.com>
