In driver file flash_stm32wba_fm.c, rename ble_ctrl_work_q
to ble_ctle_work_q and make ble_ctle_work_q non-static
in SoC code
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add support for bad block management in SPI NAND flash devices.
This includes functions to check if a block is bad and to mark
a block as bad. The bad block marker is stored in the OOB area of
the first page of each block.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add Kconfig option to accept unaligned addresses and/or lengths for
flash_write for stm32 devices. Use with caution after understanding
target platform flash implementation details. Op may fault if used
without forethought
Signed-off-by: Sudarshan Jagannathan <sudarshan.jagannathan@st.com>
Fixes:
zephyrproject/zephyr/drivers/flash/flash_stm32_ex_op.c:348:3: warning:
label followed by a declaration is a C23 extension [-Wc23-extensions]
348 | int rv2;
| ^
when compiling with llvm.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Previously, nv-flash nodes were used as the flash controller and
contained APIs. But currently, to support mapped-partitions
and allow MCUboot to run on RA8x2 devices, this MRAM driver need
to correct the node that used for flash controller.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The nrf_rram_write() and nrf_rram_erase() functions were missing
input validation for address and length alignment.
nrf_rram_write() did not verify that addr and len are multiples of
WRITE_LINE_SIZE (16 bytes), allowing unaligned writes to succeed
when they should return -EINVAL.
nrf_rram_erase() did not verify that addr and len are multiples of
PAGE_SIZE (4096 bytes), allowing unaligned erases to succeed when
they should return -EINVAL.
Add alignment checks to both functions to correctly reject invalid
operations as required by the flash API contract.
Assisted-by: Claude:claude-sonnet-4-6
Fixes#102511
Signed-off-by: Mohit Talwar <talwarmohit2005@gmail.com>
Implement a device driver for XSPI manager.
This allows to define the xspi controllers configuration that should
be applied towards the xspi IO ports:
- Muxed
- Swapped
- ...
Since its configuration has impact on final application location and
implies the deactivation of xspi clocks, it should be run only at fsbl
stage and not later.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
There is no such thing as XSPIM1/XSPIM2 and not all XSPIM compatible
devices declare HAL_XSPIM_IOPORT_1/2.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The PSOC4 flash driver accepted unaligned write offsets and sizes,
using a read-modify-write path to handle sub-row writes. This
violated the flash API contract, as the driver advertises
write_block_size=256 via devicetree.
Additionally, the Infineon HAL function Cy_Flash_WriteRow() requires
row-aligned addresses and exactly CY_FLASH_SIZEOF_ROW bytes of data.
The R-M-W path was passing unaligned addresses to the HAL, which
would reject them, but the driver was not checking the return value
and silently reported success after failed writes.
Add write alignment validation for both offset and size. Remove the
dead read-modify-write code path. Add missing error checking on
Cy_Flash_WriteRow() return value in the write loop, consistent with
the erase function.
Handle caller-provided data buffers that are not 4-byte aligned by
staging each row through a local aligned buffer before calling
Cy_Flash_WriteRow(), which requires a uint32_t-aligned source
pointer. When the source is already aligned, it is passed directly
with no copy overhead.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Memory W25Q256 support added into flash driver. If someone
uses this memory, the driver will configured into 4-bytes
address mode which will cause issues with the bootROM for
some NXP's RTs/RW microcontrollers.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
Name the XSPI 1/2 depending on the stm32 series. It could be mixed between
XSPI or OCTOSPI depending on the module HAL.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On mcxw70, the flash cache is managed by the underlying driver from
hal_nxp. The method used in the soc_flash_mcux driver is not suitable
for this platform, and should be disabled.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
NAND flash translation layers require the flash extended operations API
for bad block management. Add it here without implementation to test an
FTL on the flash simulator.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Add extended operations to the flash API to support marking blocks
as bad and checking if a block is bad. This is necessary for
NAND flash devices, which can have bad blocks that need to be managed.
Signed-off-by: Pascal Linder <pascal.linder@zuehlke.com>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Replaces usage of these deprecated macros with ones that support
fixed and mapped partition compatibles. Also includes an update to
hal_espressif which also (rightly or wrongly) has zephyr specific
code in it
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add dependencies for the dt props for the
SPI_NOR_SFDP choice.
Also removes the no no longer needed build asserts.
Nice benefit is, that we fallback to SPI_NOR_SFDP_RUNTIME,
if the required dt props for the other options are not set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Rename FLASH_SIZE(inst) to FLASH_SIZE_INST(inst) and
FLASH_PAGE_SIZE(inst) to FLASH_PAGE_SIZE_INST(inst) in
flash_mspi_nor_sfdp.h to avoid redefinition conflicts with
STM32 HAL headers (stm32l562xx.h and stm32l5xx_hal_flash.h).
Note: Several HAL STM32 files use this macro naming convention;
this issue is not specific to STM32L5.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add an opt-in Kconfig option to use the RP2350 untranslated XIP alias
for flash reads. This ensures the flash API can still access physical
partitions when Address Translation has remapped the primary window.
It otherwise introduces no changes for existing applications.
Signed-off-by: Raul Hernandez <raul.hernandez@spaceface.dev>
Update the @param documentation for qspi_npcx_fiu_uma_block to match the
actual function signature, changing lock to lock_en.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
The simulated flash driver incorrectly applied the no_explicit_erase
capability. It was overriding Kconfig settings with a missing Devicetree
property, which caused RAM-like configurations to wrongly report needing
explicit erases before writes.
This commit fixes the initialization macro to correctly check the DT
instance property no-explicit-erase, while properly falling back to the
global CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE Kconfig.
A new runtime test is also added to properly verify this capability.
Fixes#100352Fixes#100400
Signed-off-by: Seyoung Jeong <seyoungjeong@gmail.com>
The check for the layout size, when CONFIG_SPI_NOR_SFDP_DEVICETREE
is enabled, is already done with build asserts during build
(inside PAGE_LAYOUT_GEN). We don't need to check a second
time.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The parsing of the number of bytes to read in the read command was being
done in hexadecimal, causing unexpected behavior.
Now the number can be interpreted in decimal or hexadecimal if prefixed
with 0x.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
This patch avoids the use of the default device on destructive
operations like erase and write. Allowing it might have catastrophic
results like erasing parts or the whole of the application itself.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
The parameter page is not ECC protected, but can return ECC errors under
some conditions. These errors should be ignored so drivers can
initialize.
Signed-off-by: Atilla Filiz <atilla@fi-tech.be>
MRAM programs via direct memory-mapped writes, which the ARM MPU
blocks unless MPU_ALLOW_FLASH_WRITE is enabled. Fixes a Data Access
Violation on ra8x2 when running the flash common test suite.
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
When IPED encryption is enabled, AHB-mapped reads can hang.
Switch flash_flexspi_nor_read() to use FlexSPI IP read
transactions and handle unaligned requests with aligned
chunk reads plus memcpy to the caller buffer.
This removes the SoC-specific workaround and avoids
hangs in encrypted regions.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Add support for reset extended operation to clear all volatile register
settings. Notably, ECC enable and block protection registers are not
reset by a soft reset.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
- Get unit number and memory size from devicetree
- Renesas RZ/T2L uses at25sf128a flash chip which differs from RZ/T2M
and RZ/N2L supported previously. The Write Status Command may write
incorrect data to Status Register or Configuration Register on this
chip. Remove this code to make the driver common for other SoCs.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
On the stm32U3 with 512K of flash in a single bank,
reset the BKER bit of the FLASH_CR register.
See RefMan Table Flash module organization"
Note "2. When DUALBANK is set to 0 in the option bytes,
for 512-Kbyte single-bank STM32U375/385 devices,
the flash is addressed as a single bank,
and the page numbers are continuous from 0 to 127.
Set BKER = 0 to select bank 1."
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3 series, erase/program operation requires
the voltage range is set to range 1.
This is done before loop on erase/write and the initial voltage
range is restored afterwards.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3, like it is on the stm32U5 series,
gives the exact nb of pages of 4KB depending on the flash size.
For the page layout, the nb of pages does not depends on the
DUALBANK option byte.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add FM_Init() function call in the Flash driver initialization
to initialize the Flash Module.
This function is introduced by the STM32Cube_FW_WBA_V1.8.0
release.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add CONFIG_FLASH_MSPI_NOR_DMA_DATA_XFER and
CONFIG_FLASH_MSPI_NOR_DMA_CONTROL_XFER as Kconfig options for MSPI
NOR Flash driver. These options are used to select whether data and
control transfers should be performed using DMA or PIO modes.
Update flash_mspi_nor to store choices and apply them accordingly:
use data-xfer-mode for read/write data transfers, and control-xfer-mode
for command/register/configuration traffic. This selection is due to DMA
transfer's having a larger setup overhead so is less beneficial for
short control transfers.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Add support for the PM API to the flash simulator. This enables testing
the PM behaviour of higher level libraries that use PM in CI to ensure
there are no missing/excessive calls to `pm_device_runtime_put` by the
library. For example:
```
ZTEST(library_pm, test_pm_calls)
{
const struct device *flash = DEVICE_DT_GET_ONE();
zassert_equal(0, pm_device_runtime_usage(flash));
some_complex_flash_user();
zassert_equal(0, pm_device_runtime_usage(flash));
}
```
Signed-off-by: Jordan Yates <jordan@embeint.com>
HSLV now handled by stm32_iocell driver and board device tree.
LL_PWR_EnableXSPIM2 called already in SoC initialization:
soc/st/stm32/stm32h7rsx/soc.c
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Make use of a default 1ms value to reset_gpios_duration.
Do not put default to dt prop reset-gpios-duration since it should remain
optionnal.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
