Some flash/memc drivers like flexspi will want to default the
value of the log level to off to avoid RWW hazard while XIP,
to do this, the logging template must be sourced after the driver
kconfig files so that the default value from the driver is able
to be checked, since logging template introduces an unconditional
default otherwise.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Use the define to send the reset cmd at quad-flash init :
SPI_NOR_CMD_RESET_EN followed by SPI_NOR_CMD_RESET_MEM
when the st,stm32-qspi-nor has the <reset-cmd> property set.
Reports the jedecID correctly.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove dead code. The write opcode instruction
is set based on dev_data a couple of lines after.
This was supposed to be in the merged "memory map
support for other modes" PR.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
When application code runs from M4 (resides on lower 896KiB of
the internal flash of bank2) and it does write to a block in
the upper 128KiB, write fails sometime (for example failed
1 out of 10 block write based on the tests) due to STRBERR.
As per technical reference manual section 4.7.4 of
STM32H745/755 SoC, application may ignore this error and
continue with write. So check for the flag and return okay
status for write(). Based on our tests, the application write
succeeds even when this error happens and match with document
description. So igoring this error flag is okay during write.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Add more clarity to memory map log output.
Use LOG_DBG instead of LOG_INF to signal about
memory map mode being enabled.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
RRAMC peripheral is a secure-only peripheral, and the application
cannot use it directly. While building an application with TF-M
enabled and SOC_FLASH_NRF_RRAM the NRFX_RRAMC selection must
be forbidden.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
This variable is only used under DUAL_BANK condition and a warning
is generated in !DUAL_BANK case, so move its definition accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
When QSPI configuration is the dual-flash, the total
flash size and erase size are doubled. This is handled
with a STM32_QSPI_DOUBLE_FLASH factor which doubles
the values of one qspi component.
Note that SFDP table is for ONE flash component.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The offset is wrong when the second bank is used by M4 as the
offset is relative to the base which is 0. So add the least
significant 6 nibbles from the CONFIG_FLASH_BASE_ADDRESS to
find the sector.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
When using SPI-NOR SFDP autodeteection, the flash size printed to
the log is rounded to 1 MiByte. If flash is smaller than 1 MiByte
it is printed as 0 MiByte.
With this patch smaller flash sizes are printed in kiByte, for instance
512 kiByte is printed correctly.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Device drivers should not be calling `pm_device_runtime_enable` on
themselves, it should be left up to the application. If automatic
enablement is desired, `zephyr,pm-device-runtime-auto` exists as a
devicetree property.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `pm_device_runtime_get` and `pm_device_runtime_put` functions work
correctly regardless of whether `PM_DEVICE_RUNTIME` is enabled or not.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `count` semaphore was being used as an atomic counter, so replace
it with an atomic variable, which is a simpler solution and enables
removing the conditionals with `PM_DEVICE_RUNTIME`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
PR #63973 namespaced generated headers with zephyr/, including generated
syscall headers.
Since then, some new generated syscall header includes have been added
without the zephyr/ prefix, breaking builds when
CONFIG_LEGACY_GENERATED_INCLUDE_PATH is disabled.
This commit adds the zephyr/ prefix to includes for generated syscall
headers where it has been missed.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Add check for returned value from the call to spi_nor_cmd_write
in spi_nor_write.
Fixes#74775
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Adding the support of the memoryMapped mode
to the flash_stm32_xspi driver through the CONFIG_STM32_MEMMAP
That will allow XiP from the external octo_flash
Erase and Write operation must Abort operations.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Erasing rram is very similar to partial erase on flash.
So we should use the same multiplier as there, 1.5.
0.1 multipler is way to low and was causing timeouts.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add support to select the nCS line for XSPI from the device tree.
Disable the nCS override.
This setting only works with series that have an XSPIM (so not H5)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the support of the stm32h7rs serie to the flash stm32h7 driver
Remap Flash registers to the stm32h7rs serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32 flash driver returns success even though
writing failed when instruction cache was enabled.
Fix by not overriding error code when re-enabling
instruction cache.
Signed-off-by: Riku Karjalainen <riku.karjalainen@vaisala.com>
Refactor the `QSPI_CommandTypeDef cmd_write_en` definition to
a `static const` local variable to eliminate redundant definitions.
This change enhances performance by reducing runtime overhead associated
with initializing `cmd_write_en` in multiple functions.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add the commands to read and write to/from the xSPI with gpDMA
On the stm32h5 device, the one request for xspi instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure the xspi clocks domain by the clock domain
as defined by the DTS
Up to 3 possible clock confg : xspix, xspi_ker, xspi_mgr
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix compilation error when reset-gpios is enabled.
Undefined reference to dev_cfg variable.
Reset gpio duration needs to be defined, but is not in binding file.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Move STM32_MEMMAP outside of SOC_FLASH_STM32.
That allows memory-mapped application to
be built without internal flash controller.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Configure the quad-spi in DualFlash Mode when enabling the MemoryMapped
then reading is possible with memcopy.
DUAL flash mode is possible on stm32 series with QUADSPI_CR_DFM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Incorrectly placed preprocessor conditions caused exit_dpd
when there has been no instance of a device with
dpd_wakeup_sequence parameter.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Signed-off-by: Jan Tore Guggedal <jantore.guggedal@nordicsemi.no>
