The FlexSPI NOR driver should verify all 3 bytes of the JEDEC ID match
the expected value before attempting to use a custom LUT table with a
flash chip. This reduces the odds that an incompatible LUT will be used
with a flash chip, as some flash chips may share the same first byte of
their device ID but not be compatible with the custom LUT table.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
some flashes support special opcodes
for 4-byte addressing, that can be used
without switching to 4-byte mode.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The flash_flexspi_nor_check_jedec() checks the lower 16-bits of
the manufacturer ID and installs a custom LUT table.
Add an exception to check for the whole 32-bits so we do not
accidentally install custom LUT for flash devices that do not
support this LUT table.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The CONFIG_PINCTRL is removed from the board's defconfig files.
Drivers which use pin control function should add "select PINCTRL"
in their Kconfig files.
Fixes#78619
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The current alignment logic does not work as expected if given unaligned
values, resulting in a skip of the first word. The length also has to
take into account the starting address: for example, asking for 2 bytes
at offset 3 should actually check 8 bytes.
This patch adjusts the logic so that it always includes the first and
the last word of the input area.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
As other targets in the LPC55xxx series, the LPC55S36 has a Flash
controller that raises ECC errors when reading erased pages directly.
To avoid this, there is special code for this platform that calls the
HAL FLASH_IsFlashAreaReadable() function. However, this in turn calls a
function at an hardcoded address in ROM that _always_ causes an
instruction fault, making the situation worse.
This patch reworks the read operation to use the FLASH_Read() HAL
function for this target to gracefully handle error conditions and
properly emulate accesses to erased pages. The preprocessor is required
since some targets do not define the FLASH_Read() function.
Fixes: #80325
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Not all the stm32H7 have a clock enable for their flash;
only the dual-core.
For the st,stm32h7-flash-controller with "clocks" property, the driver
will enable the flash clock bit in the corresponding RCC register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The struct jesd216_bfp was declared as __packed but later in the code
the address of a member was given to a non-packed pointer, potentially
causing reading of wrong addresses, and causing warnings with the
IAR ICCARM compiler.
After studying the JEDEC documentation JESD216F.02, section
6.4.2 JEDEC Basic Flash Parameter Header: 2nd DWORD, the struct must
be aligned to 4 so __packed is not necessary, just 4 byte alignment.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
lots of values from the DT where not set corretly, if
`CONFIG_SPI_NOR_SFDP_RUNTIME` was
enabled. This fixes it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
IS25LP flash chips have a similar P[6:3] register to the IS25WP series,
and need the same workaround.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some NXP boards program the read parameters bits (P[6:3]) within the
IS25WP flash device during init, which will result in JESD216 probe
commands failing (as the number of dummy cycles will be incorrect). Add
handling to force these volatile bits to their default value to the
flexspi flash driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Quad enable method 5 reads status register 2 (one byte), but then writes
to 2 bytes to the status registers, so we need to shift the output
buffer in order to manage this correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Writing the quad enable bit on flash chips typically requires a write
enable instruction be issued before writing the non-volatile status
register, and the flash may remain busy briefly after programming this
bit. Add code to send the WREN instruction, and to wait for the flash to
finish programming after writing the status register.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move the LUT used for probing to be stored in .data, instead of on the
stack. This reduces stack usage during probe by 192 bytes, which avoids
stack overflows that were occurring on some platforms.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix build of nrf_qspi_nor flash driver without multithreading enabled.
This is required for builds like mcuboot.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
IAP is a reference to the method of software interaction with the flash
used in the current driver implementing support for this flash. The
DT compatible should not be named like this.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a flash copy command, capable of copying a region in one
flash device to a region on the same or another flash device. The
destination is erased prior to copying.
This is useful for evaluating mcuboot on devices with little
on-chip resources, or devices that are incapable of running more
elaborate image management services (e.g. via bluetooth or
networking).
Additionally, it's useful for evaluating mcuboot on devices with
one or more images stored on external spi flash.
The command syntax is
flash copy <src_dev> <dst_dev> <src_offs> <dest_offs> <size>
E.g.
flash copy flash@0 flash-controller@abcd1234 0x1234 0x5678 21012
Copied 21012 bytes from flash@0:1234 to \
flash-controller@abcd1234:5678
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Provide a generic flash_copy() algorithm that is capable of
copying from one flash device to another or within different
regions of the same flash device.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
The flash simulator assumes that flash is being addressed with absolute
addresses by clients. But this is not the case. Given addresses are
relative to the flash base address.
The existing code only worked because the base address was always zero.
Testing with non-zero base addresses caused a mem fault/page fault.
(Reproducible e.g. when using the NVS settings subsystem on QEMU x86
with a non-zero base address in the soc-nv-flash node.)
Fixes#79082
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add the write_unprotect command to the stm32 qspi flash driver
to un protect flash before any write operation to the external quad-NOR
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the support of the requires_ulbpr property when a Microchip
quad-spi flash is mounted.
Set the CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32=y flag to access
the command
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Some applications may require the SPI NOR driver to be initialized
earlier. This commit enables the user to change the default
initialization priority.
Signed-off-by: Vidar Berg <vidar.berg@nordicsemi.no>
The CONFIG_PINCTRL setting is removed from the board
_defconfig files. And "select PINCTRL" is added to
the appropriate driver files.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
