The goal of this patch is to switch from the nwp.c and nwp.h soc files
to the new nwp driver. During this transition, we also renamed
CONFIG_WISECONNECT_NETWORK_STACK to CONFIG_SILABS_SIWX91X_NWP which are
a better naming to let the user knows that the network coprocessor files
will be added to the compilation.
The switch from a soc file to a driver device introduce a notion of nwp
device that allows us to check for good initialization and ressources
allocation.
Before this patch, it is not possible to know if the nwp have booted
successfully or not. We can now check if the device driver is ready
or not before trying to do operation related to the nwp.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Commit 76740ae added a special case to the STM32 QSPI driver to support
Microchip QSPI flash ICs, such as the SST26VF series,
which use the PP_1_1_4 opcode in PP_1_4_4 mode.
This commit adds the same special case to the STM32 OSPI and XSPI drivers.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Commits 72370b2 and ff34d57 added the requires-ulbpr
(Unlock Block Protection Register) property to the devicetree binding
for devices controlled by the STM32 QSPI peripheral, and support for
this property to the STM32 QSPI driver.
Some QSPI flash ICs (e.g. Microchip SST26VF series) require this
command to be sent before writing/erasing is possible.
This commit adds the same support to the STM32 OSPI and XSPI drivers.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Use information provided in the dts node for the MSPI controller
regarding maximum amount of data that can be transferred in one
packet and split the requested transfers if necessary.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Revert a change that broke the stable API function shell_set_bypass.
This reverts commit 6b876dba1ba61b659b1b2d4c3ccd0ac41bd56027.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Commit 539928d introduced a special behaviour for Microchip QSPI flash
memories into the STM32 QSPI flash driver, to handle the fact that these
memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation
(usually 38H).
The special Microchip-specific behaviour introduced in that commit sets
the address mode for a QSPI 1-1-4 write operation to 4 address lines,
rather than 1 address line, when the write command is configured as
SPI_NOR_CMD_PP_1_1_4. If the write command is configured as
SPI_NOR_CMD_PP_1_4_4, nothing is done and the operation will not succeed.
This behaviour is a bit backwards, as it results in a QSPI flash memory
configured in 1-1-4 write mode using 4 address lines (1-4-4 operation).
It should be the other way round, so that a QSPI flash memory configured
in 1-4-4 mode uses 4 address lines (1-4-4 operation).
This commit changes the Microchip-specific special behaviour to set the
opcode for the specified write mode, rather than using a different write
mode to that which is configured in order to use a valid opcode. This
means that a QSPI flash memory configured in 1-4-4 mode, or without the
writeoc DT property set (defaults to 1-4-4 for quad mode), will operate
in 1-4-4 mode. 1-1-4 mode is unsupported, as before.
Also update the Kconfig option description for
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32 to remove references to the
Global Block Protection Unlock instruction - this was added at the same
time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4
opcode but is distinct from this and is not affected by
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Allow passing some context to the shell bypass callback function by
providing a void pointer user data argument.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The DDR LUT entry for ERASE_CHIP was configured with an incorrect
kFLEXSPI_Command, resulting in the erase operation not being executed.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
The maximum speed should be configured individually for each board
since it depends on the layout and the controller's flexspi capabilities.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG
and had a wrong value for READ.
The default amount of dummy cycles on this chip are 20 (0x14).
This means the LUT should contain the value of 0x28 (0x14*2) for DDR
at these entries.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Implementation based on STM32G4 series.
This is a preparation to enable reading and writing the RDP bits.
Signed-off-by: Martin Jäger <martin@libre.solar>
1. Introduced GDMA support for efficient data transfer in the
NPCX FIU QSPI driver.
2. Refactor flash driver mutex handling to enhance concurrency safety,
preventing other threads from preempting erase/write operations during
UMA until mutex release.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
If the process does an exec() (or fork, or..) all descriptors are kept
open by default, unless O_CLOEXEC is set when opening them.
This is usefull for stdin/out/err so that new process is connected to
them, but it is very rare for it to be usefull for any other descriptor.
In general this leads to descriptors being kept open unnecessarily,
which either will block other process from getting them (for example
if the child survives the parent but it does something else).
Or for a "leak" which unnecessarily uses descriptors and memory in the
child process.
Let's ensure we do not leak it for this component as we do not need it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add possibility to use the driver in configurations with disabled
multithreading. It may be useful in bootloaders, for example.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
write enable already happens in the write/erase loop
before every write and erase. It is done in the loop,
because it is self cleaning after erase and write.
That is also the reason we don't need to disable it,
as it is automatically disabled after each write and erase.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The only information for 4s-4d-4d, 8s-8s-8s and 8d-8d-8d in the basic flash
parameter table is in DWORD20 with one byte for each of the aforementioned
modes. This one byte is split into two fields that contain that mode's
maximum operation speed with and without data strobe. Unsupported fields
have the value of 0xF. For the mode to be supported, at least one of the
two fields must not be 0xF, so we check the byte against 0xFF.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Ensuring flash region has been erased before writing to avoid
inconsistences and force expected erased value (0xFF) into
flash when erasing a region when Hardware Flash Encryption is
enabled
This is handled on this implementation because MCUboot's state
machine relies on erased valued data (0xFF) readed from a
previously erased region that was not written yet, however when
hardware flash encryption is enabled, the flash read always
decrypts whats being read from flash, thus a region that was
erased would not be read as what MCUboot expected (0xFF).
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Adjust the bit field check sequence for "en4b" to support some flash
devices that offer multiple mechanisms for entering 4-byte address
mode.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Some applications need to throttle RRAM writes to handle peak current
management.
Add CONFIG_NRF_RRAM_THROTTLING_DATA_BLOCK which defines the maximum
chunk length that can be written at once.
Add CONFIG_NRF_RRAM_THROTTLING_DELAY which configures the sleep delay in
microseconds after each write.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
The jedec-id cannot be read after flash device is set to octal mode.
Fixed by moving the jedec-id comparison to
flash_flexspi_nor_check_jedec() which already reads the jedec-id when
flash device is still in single spi mode.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Some devices supported by this driver do not have a write-block-size
of 1 such as the mt35xu01gbba. This value is assigned in the dts and can
be used instead.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Fix stm32 XSPI driver to restore the bus command concurrent access
protection that was mistakenly removed on memory mapping operation
by commit e5620e07c9 ("drivers: flash: stm32 xspi flash read with
memcopy when executing").
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This is a follow-up to commit cafa288197.
Bit masks should use the bitwise OR operator, not the logical one...
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
When Octal IO mode is to be used with DDR in mx25u family chips,
bit 1 instead of 0 must be set in the Configuration Register 2 at
address 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for supplying power to the flash chip by activation of
a GPIO specified through the "supply-gpios" property. Implementation
of gpio_reset() is also slightly modified so that it is consistent
with soft_reset() and the new power_supply() and so that all these
functions can use a common routine that performs a reset recovery
delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Using a GPIO reset for a flash chip that has a dual function pin
(RESET# or SIO3) and is to be used in Quad mode is rather a bad idea
and so is clearing of the Quad Enable bit at every initialization
of the flash driver, since this bit is usually non-volatile, so such
operation means unnecessary wearing of the flash chip. Soft Reset
should be use instead in such case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add implementation of the most common Soft Reset routine (sequence of
reset enable instruction 0x66 and reset instruction 0x99).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Complete implementation of quad_enable_set() by adding support for all
possible Quad Enable Requirements (QER) as specified by the SFDP JEDEC
standard (JESD216). Add also corresponding octal_enable_set() to handle
Octal Enable Requirements.
Also remove initial waiting from mxicy_mx25r_post_switch_mode() which
became unneeded, as now such waiting is done in cmd_wrsr() which is
called at the end of quad_enable_set().
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Use standard operation codes and parameters from SFDP for handling
the used flash commands (allow to override some of them through dts
with the `read-command`, `write-command`, and `rx-dummy` properties)
- Use all available erase types as specified by SFDP
- Allow using all IO modes
- Add support for switching to 4-byte addressing mode
- Use common functions for reading and writing of status registers
and for enabling write operations
- Switch IO mode (between the target one and Single IO) in a common
function that performs transfers and do it only when required for
a given command
- Make checking of JEDEC ID at initialization optional
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Get parameters for used flash commands and requirements for enabling
Quad and Octal modes from dts uint8-arrays containing data read from
SFDP tables for particular flash chips.
Also introduce `pre_init` quirk that allows alteration of the above
parameters or complementation of them in a specific way for particular
flash chip families.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Asynchronously release the device after a small delay to minimise power
state transitions under multiple sequential API calls (e.g. NVS).
Signed-off-by: Jordan Yates <jordan@embeint.com>
According to the datasheet, one page is made of 64 bytes
and one row is made of 4 pages, that is 256 bytes.
This MR fixes the incorrect page write size for sam0
and sets it to 64 bytes.
Signed-off-by: Taras Zaporozhets <zaporozhets.taras@gmail.com>
The following error is issued by clang when building with
SPI_NOR_SFDP_RUNTIME enabled:
error: fields must have a constant size:
'variable length array in structure' extension will never be supported
1379 | uint32_t dw[MIN(php->len_dw, 20)];
Instead, hardcode the array length to 20 32-bit words (it's instantiated
in the stack anyway).
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
In HAL based stm32 drivers, dma handling is done internally to HAL.
Though, in order to avoid a dma_config() call is done to ensure stream
will be set as busy in zephyr dma driver to avoid potential resource
sharing conflict.
This dma_config() call was done while taking into account
STM32_DMA_STREAM_OFFSET, which is wrong as it will prevent zephyr dma
driver to set the right stream as busy.
Fix this in impacted drivers.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The AT25XV021A variant is a flash variant of Atmel's AT25 family
that adds extra protections, requiring additional writes to the
device to program or erase data.
This commit adds a flash driver for AT25XV021A devices instead of
modifying (1) the existing AT45 SPI flash driver or (2) the
existing AT24/25 EEPROM driver because this variant poses
fundamental changes that affect all aspects of the driver.
Notably,
- AT25XV021A includes a second status register, and the format
and functions of the existing status register is
changed from the existing drivers.
- AT25XV021A requires executing page or chip erase commands
before writing, making it incompatible with the
existing AT24/25 EEPROM driver.
- AT25XV021A adds a software protection layer that requires
extra writes before executing program or erase commands.
Tested writing to and erasing from an AT25XV021A device. Tested
reading from an AT25XV021A device across page boundaries. Tested
chip erase function. Tested driver initialization from varying
initial hardware states.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
This commit is fixing configuration of mx66uw1g45g NOR when working
at 200MHz.
According to its specification, when running at 200MHz, this memory should
use a Number Dummy Cycles configuration of 20 (DC bits in CFGR2), which is
the device's default configuration.
Applying the 66MHz configuration as done today was preventing flash to run
at frequency higher than 100Mhz.
This commit doesn't solve the more generic problem of this driver which
is applying this 66MHz configuration universally, irrespective of the
frequency and the memory device, but fixes the configuration which was
reported broken today.
Providing a global change would require starting a clear split between XSPI
controller configuration an bus device configuration, which is what new
MSPI API intend to solve, so this will be tackled once this driver will be
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
When the application is executed in external flash, the read operation
cannot be in indirect mode but with memcopy.
Note that writing or erasing the external flash being executed
is not possible during the execution.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Commit df0f74d491c851b3e7e970f898c5c2fc3aab5b80 added a shell command to be
able to print out the partitions. However the label property is optional.
Print both the name and label if available.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
