Add support for flash to cc23x0 SoC. The driver interacts with VIMS
(Versatile Instruction Memory System) internal bus standing before NVM.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Added area_is_subregion() to validate offset and size within bounds.
Ensured read, write, and erase operations check for valid memory regions.
Added null buffer check in read and write functions to prevent errors.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Make sure to submit a change of option bytes and wait for the end of
the operation. It is done by checking the OPT_BUSY bit.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The RDP level is set with the FLASH_OPTSR_PRG register and read with the
FLASH_OPTSR_CUR register, not FLASH_OPTCR.
Fix that to realy change and read RDP.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add support HyperFlash memory devices on a NXP S32 QSPI bus.
This driver uses a fixed LUT configuration that defined in HAL RTD
HyperFlash driver.
Driver allows to read, write and erase HyperFlash devices.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Remove the #ifdef guard around a function prototype. This was causing a
compile error when CONFIG_FLASH_NPCX_FIU_DRA_V2 was disabled.
Signed-off-by: Keith Short <keithshort@google.com>
Exit the init earlier when XSPI is in memory map mode. Avoid
unnecessary checks and prevent pin reconfiguration that might
cause line spikes. Clock check beforehand is preserved.
Remove '\n' from the LOG_DBG string.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Exit the init earlier when OSPI is in memory map mode. Avoid
unnecessary checks and prevent pin reconfiguration that might
cause line spikes. Clock check beforehand is preserved.
Remove '\n' from the LOG_DBG string.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
After writing option bytes, force them to be loaded. Failing to perform
this step means the values are never applied and not actually written
to non-volatile memory.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Do not unlock CR at the end of initialization.
The lock mechanism is to protect unwanted registers modifications due to
software bugs. There is no point in leaving the registers unlock once
the driver is initialized.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The CMD_BLANK_CHECK can return errors when the flash is readable, and
should only be used after programming, not in is_area_readable(). From
the LPC55S69 datasheet: "As cells age and lose charge, a correctly
programmed address will fail this check, while still being able to be
read successfully for the remaining duration of the data retention time."
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use uint64_t instead of uint32_t for the FLASH_STM32_EX_OP_SECTOR_WP
extended operation.
Some chips have two banks, more than 16 sectors each e.g. stm32h7a3xx
chips, so more than 32 bits are required.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
XIP prefetching seems to still be running, even while interrupts are
disabled. Therefore it is important to wait for the FlexSPI to be idle
before performing a write/erase operation.
Signed-off-by: Martin Stumpf <martin.stumpf@vected.de>
Enable buffered write for nRF54l RRAM flash driver by default.
CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE=1 means that write will be buffered
by 16 B buffer (native RRAM write-bock-size).
This allows optimal life-endurance of RRAM memory.
For reference" DTS declares 16 write-block-size already.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Adapt the stm32 flash driver for the stm32h7rs serie where some
bit of the FLASH registers are named differently from stm32h7 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use shell_device_get_binding() instead of device_get_binding() so that
we get the device based on its name and in addition by its label.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
When the CONFIG_BT_STM32WBA the stm32wba_fm flash driver is compiled
and must takes flash_stm32_sem_take/give functions from the
flash_stm32.h header file, like other stm32 series.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add two new flash extended operations for reading and writing STM32
option bytes from the application code.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Currently, MT25 flashes were running in 3-byte mode.
This is not compatible with the chip we use in our project (MT25QU01GBBB),
as only 128 Mbit of its 1 Gbit can be addressed.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
Implement the readout protection for the STM32H7 series.
Define the specific functions used by the flash_stm32h7.
Move the stm32h7 flash register manipulation in a write_optb()
to be called by the flash_stm32_set_rdp_level.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Place the flash_stm32_sem_take and flash_stm32_sem_give
function to header file for common to use in any flash driver
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The FlexSPI NOR driver should verify all 3 bytes of the JEDEC ID match
the expected value before attempting to use a custom LUT table with a
flash chip. This reduces the odds that an incompatible LUT will be used
with a flash chip, as some flash chips may share the same first byte of
their device ID but not be compatible with the custom LUT table.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
some flashes support special opcodes
for 4-byte addressing, that can be used
without switching to 4-byte mode.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
