Add the 4Bytes program mode to the stm32_ospi driver
to enter 4-Byte Address Mode (SPI_NOR_CMD_4BA) when flash is supporting it.
This is given by the JESD216 SFDP table.
Based on the stm32 qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The value read from unwritten areas of Renesas RAxxx SoCs data
flash is undefined. To prevent reading unwritten areas a
blank check command is performed first. If the area is blank, we
return dummy data so it behaves the same as other flash devices.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
In hal_stm32 commit "update stm32h7rs to cube version V1.2.0"
e5eba65b76
the constants FLASH_OPTKEY1/2 for the STM32H7RS have been renamed to
FLASH_OPT_KEY1/2. For backward compatibility, 2 defines have been added
to Legacy/stm32_hal_legacy.h, so that FLASH_OPTKEYx is an alias for
FLASH_OPT_KEYx.
However, in Zephyr's STM32 flash driver, the alias is defined the other
way around since 5dc537389a, which leads to
Twister build failures, for example
https://github.com/zephyrproject-rtos/zephyr/actions/runs/14927867714/job/41936931524#step:12:1335
To fix the build issue, we can simply remove that alias in Zephyr, since
it is no longer needed.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Since https://github.com/zephyrproject-rtos/zephyr/pull/83114 was merged,
I get twister errors unrelated to my pull requests for the STM32H7S78-DK
(for example https://github.com/zephyrproject-rtos/zephyr/actions/runs/14900504138/job/41851537049#step:12:1369)
This is because the function LL_GetFlashSize() was removed from hal_stm32
on the STM32H7RS series in
e5eba65b76
I am unsure if the removal from hal_stm32 is intentional. If yes, then this
commit should be merged into Zephyr to fix compilation for that target.
Otherwise, hal_stm32 must be patched, Zephyr's west manifest updated, and
this commit can be discarded.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Add the MSPI controller support for apollo5x.
Add the MSPI controller to mspi API test.
Updated west.yml for hal updates.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
1. Moved ambiq specific macro to mspi_ambiq header.
2. Always fill rx&tx dummy settings regardless of transfer direction.
3. Add the CONFIG_MSPI_* macro for optional features.
4. Fixed the ID read process and add k_sleep during busy_wait in
atxp032 driver.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Use the LL_GetFlashSize to retrieve the size of the flash, reading the
system flash OTP of the stm32h5 serie. This operation requires
Icache disable/re-enable to access the 0x08FF F80C memory area
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement the get_size flash device API function for the various stm32
This is just CONFIG_FLASH_SIZE expressed in Bytes or the FLASH_SIZE
given by the LL driver
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move the flash_stm32_write_protection and
flash_stm32_option_bytes_lock functions to a common
file for stm32 devices including stm32h7
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace the assert on the value of the prescaler by a standard check and
an error value return (similar to the STM32 XSPI PSRAM driver).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Since the Dual Mode feature doesn't actually work when selected,
and we also realize that we can't support key features of dual
mode, such as bank swap using hardware.
As a solution, we desire to remove this Dual mode feature.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
New property of the st,stm32-xspi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-xspi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove XIP dependency for enabling memory mapping for Q/O/XSPI NOR Flash.
It is not necessary and is preventing configuring an external Flash in
memmap mode if there is no internal Flash (like on STM32N6)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The current shim driver for flash-nxp-s32-qspi returns invalid error
when handling write, erase operations with zero size.
This issue causes the failure of the tests/subsys/settings/fcb/.
Updated to ignore the flash operations with zero size instead of.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Commit 857e5793f1 fix
the flash_mcux_flexspi_nor.c driver to wait for the
FlexSPI to be idle before performing write/erase
operations. Add a similar check to these drivers that
also use the FlexSPI NOR block.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add a simple non-XIP transaction before deactivating the QSPI after
a XIP transaction is performed. This prevents a CPU hang from occuring
when another XIP transaction is attempted after the QSPI is activated
again.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use cache API for disabling and enabling ICACHE. The driver handles waiting
for ongoing cache invalidation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Move MSPI NOR commands to rodata.
Replace array with empty padding (~1kB) with macro-based assignments.
Ref: NCSDK-32779
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Extend driver to support single lane and 1-4-4 IO modes.
Move flash chip quirks to a separate file.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Based-on-patch-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
-The stm32wba6x has Dual Bank memory. Change the flash driver
to support this OPTion given by presence of the
DUAL_BANK bit (21) in the FLASH_OPTR register.
-Flash erase with 2 banks: Add the control of the BKER
bit of the FLASH_NSCR1 to select BANK1 or 2 of
the internal flash depending
on the page number >127 for BANK2
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The LL_GetFlashSize function has been removed for
this new HAL H7RS release. Retrieves the value now from
the devicetree using the DT_REG_SIZE macro.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
IS25LPXXXD uses the same jedec-id as IS25LPXXX, but the latter has
an extended read register, similar to IS25WPXXX. This change will
attempt to read the extended read register to determine what the
appropriate initialization value for read register should be.
Signed-off-by: John Barbero Unenge <git@lsrkttn.com>
This commit adds the possibility to add additional custom
context for flash operations for usage by non-standard
flash drivers.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The implementation for erasing pages in the flash_sam.c driver
indicated a successful erase after exceeding the last page to be
erased successfully. Since the last page has no proceeding page,
the succeeded status was not set.
This fix switches around the status to be set as succeeded before
erase begins, to have the succeeded status cleared if page unlock
or erase fails.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add low-power-write property to MSC device tree node, set
MSC_WRITECTRL_LPWRITE if enabled.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Introduce separate flash driver for Silabs Series 2. This driver
is forked from the Gecko flash driver with no changes outside of
formatting and naming.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a flash driver intended to handle various flash devices
connected over MSPI bus as long as they support JEDEC SFDP.
This is an initial commit providing only basic operations
in Octal I/O mode with some hard-coded values for Macronix
MX25Ux series chips.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Looks like 9d5ebb3cbc introduced a new warning when building with
runtime sfdp on 32 bit platforms. Fix it for good by just casting the
operation to int and go back to use %u.
Tested with:
west build -p -b gd32f450z_eval samples/drivers/flash_shell \
-DCONFIG_SPI_NOR_SFDP_RUNTIME=y
west build -p -b mpfs_icicle/polarfire/u54 samples/drivers/flash_shell
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix few printf format warnings when building for
mpfs_icicle/polarfire/e51. PRIdPTR for the pointer difference, %zu for
size_t.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Adding k_usleep while polling the flash's busy status yields the CPU
resource, giving lower-priority threads the opportunity to run.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Fix flash read operation to account for all unaligned
scenarios, i.e, address, buffer and length. This is needed
when using flash APIs provided in ROM.
This also removes the unaligned flash write call as it
expects aligned values only.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
