MCXW2XX ROMAPI provide the function FLASH_CacheClear to clear the cache.
The SMSCM is not supported on MCXW2XX platform.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the READ_BIT macro (defined in
the STM32 HAL) by stm32_reg_read_bits.
Fixes some cases where the return value was tested like a boolean
despite not being one.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Initial support Flash-LP driver for Renesas RA
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
The Kconfig symbols for selecting HAL content should be part
of the HAL module integration, not defined by the SoC. Split the
symbols between the Series 0/1 Gecko HAL and Series 2 SiSDK HAL
when moving them.
For now, the Series 0/1 HAL symbols retain their name, while new
names consistent with the symbols already defined in the module
integration layer are used for the Series 2 HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This driver is based on the XSPI driver for Renesas RZ/T2M and N2L,
and the SPIBSC driver for Renesas RZ/A3UL from the HAL.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Direct flash access can cause exceptions when performed while the flash
memory is inaccessible or being modified — for example, when code is
executing from PSRAM. To avoid such invalid access, this change introduces
asynchronous flash operations that are executed from a safe runtime context
via a work queue. This ensures all flash accesses occur only when the flash
is valid and accessible.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The STM32 QSPI, OSPI, and XSPI drivers support sending the ULBPR command
for flash ICs that require unlocking before writing to. This is done
conditionally based on the requires_ulbpr devicetree property.
Previously the driver would always log "Write Un-protected", even if a
write un-protect was not attempted. Fix this so that "Write Un-protected"
is only logged when a write un-protect is attempted and succeeds.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Extend the IT51XXX M1K flash controller driver to implement the flash
extended operation (ex_op) API. This allows runtime selection of both
the flash device and the addressing mode:
Flash target selection:
- FLASH_IT51XXX_INTERNAL: on-chip SPI eFlash
- FLASH_IT51XXX_EXTERNAL_FSPI_CS0: external SPI flash on FSCE0#
- FLASH_IT51XXX_EXTERNAL_FSPI_CS1: external SPI flash on FSCE1#
Addressing mode selection:
- FLASH_IT51XXX_ADDR_3B: 3-byte (24-bit) addressing mode, supports
flash devices up to 16MB capacity
- FLASH_IT51XXX_ADDR_4B: 4-byte (32-bit) addressing mode, required
for devices larger than 16MB
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The goal of this patch is to switch from the nwp.c and nwp.h soc files
to the new nwp driver. During this transition, we also renamed
CONFIG_WISECONNECT_NETWORK_STACK to CONFIG_SILABS_SIWX91X_NWP which are
a better naming to let the user knows that the network coprocessor files
will be added to the compilation.
The switch from a soc file to a driver device introduce a notion of nwp
device that allows us to check for good initialization and ressources
allocation.
Before this patch, it is not possible to know if the nwp have booted
successfully or not. We can now check if the device driver is ready
or not before trying to do operation related to the nwp.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Commit 76740ae added a special case to the STM32 QSPI driver to support
Microchip QSPI flash ICs, such as the SST26VF series,
which use the PP_1_1_4 opcode in PP_1_4_4 mode.
This commit adds the same special case to the STM32 OSPI and XSPI drivers.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Commits 72370b2 and ff34d57 added the requires-ulbpr
(Unlock Block Protection Register) property to the devicetree binding
for devices controlled by the STM32 QSPI peripheral, and support for
this property to the STM32 QSPI driver.
Some QSPI flash ICs (e.g. Microchip SST26VF series) require this
command to be sent before writing/erasing is possible.
This commit adds the same support to the STM32 OSPI and XSPI drivers.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Use information provided in the dts node for the MSPI controller
regarding maximum amount of data that can be transferred in one
packet and split the requested transfers if necessary.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Revert a change that broke the stable API function shell_set_bypass.
This reverts commit 6b876dba1ba61b659b1b2d4c3ccd0ac41bd56027.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Commit 539928d introduced a special behaviour for Microchip QSPI flash
memories into the STM32 QSPI flash driver, to handle the fact that these
memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation
(usually 38H).
The special Microchip-specific behaviour introduced in that commit sets
the address mode for a QSPI 1-1-4 write operation to 4 address lines,
rather than 1 address line, when the write command is configured as
SPI_NOR_CMD_PP_1_1_4. If the write command is configured as
SPI_NOR_CMD_PP_1_4_4, nothing is done and the operation will not succeed.
This behaviour is a bit backwards, as it results in a QSPI flash memory
configured in 1-1-4 write mode using 4 address lines (1-4-4 operation).
It should be the other way round, so that a QSPI flash memory configured
in 1-4-4 mode uses 4 address lines (1-4-4 operation).
This commit changes the Microchip-specific special behaviour to set the
opcode for the specified write mode, rather than using a different write
mode to that which is configured in order to use a valid opcode. This
means that a QSPI flash memory configured in 1-4-4 mode, or without the
writeoc DT property set (defaults to 1-4-4 for quad mode), will operate
in 1-4-4 mode. 1-1-4 mode is unsupported, as before.
Also update the Kconfig option description for
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32 to remove references to the
Global Block Protection Unlock instruction - this was added at the same
time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4
opcode but is distinct from this and is not affected by
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Allow passing some context to the shell bypass callback function by
providing a void pointer user data argument.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The DDR LUT entry for ERASE_CHIP was configured with an incorrect
kFLEXSPI_Command, resulting in the erase operation not being executed.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
The maximum speed should be configured individually for each board
since it depends on the layout and the controller's flexspi capabilities.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG
and had a wrong value for READ.
The default amount of dummy cycles on this chip are 20 (0x14).
This means the LUT should contain the value of 0x28 (0x14*2) for DDR
at these entries.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Implementation based on STM32G4 series.
This is a preparation to enable reading and writing the RDP bits.
Signed-off-by: Martin Jäger <martin@libre.solar>
1. Introduced GDMA support for efficient data transfer in the
NPCX FIU QSPI driver.
2. Refactor flash driver mutex handling to enhance concurrency safety,
preventing other threads from preempting erase/write operations during
UMA until mutex release.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
If the process does an exec() (or fork, or..) all descriptors are kept
open by default, unless O_CLOEXEC is set when opening them.
This is usefull for stdin/out/err so that new process is connected to
them, but it is very rare for it to be usefull for any other descriptor.
In general this leads to descriptors being kept open unnecessarily,
which either will block other process from getting them (for example
if the child survives the parent but it does something else).
Or for a "leak" which unnecessarily uses descriptors and memory in the
child process.
Let's ensure we do not leak it for this component as we do not need it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add possibility to use the driver in configurations with disabled
multithreading. It may be useful in bootloaders, for example.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
write enable already happens in the write/erase loop
before every write and erase. It is done in the loop,
because it is self cleaning after erase and write.
That is also the reason we don't need to disable it,
as it is automatically disabled after each write and erase.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The only information for 4s-4d-4d, 8s-8s-8s and 8d-8d-8d in the basic flash
parameter table is in DWORD20 with one byte for each of the aforementioned
modes. This one byte is split into two fields that contain that mode's
maximum operation speed with and without data strobe. Unsupported fields
have the value of 0xF. For the mode to be supported, at least one of the
two fields must not be 0xF, so we check the byte against 0xFF.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Ensuring flash region has been erased before writing to avoid
inconsistences and force expected erased value (0xFF) into
flash when erasing a region when Hardware Flash Encryption is
enabled
This is handled on this implementation because MCUboot's state
machine relies on erased valued data (0xFF) readed from a
previously erased region that was not written yet, however when
hardware flash encryption is enabled, the flash read always
decrypts whats being read from flash, thus a region that was
erased would not be read as what MCUboot expected (0xFF).
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Adjust the bit field check sequence for "en4b" to support some flash
devices that offer multiple mechanisms for entering 4-byte address
mode.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Some applications need to throttle RRAM writes to handle peak current
management.
Add CONFIG_NRF_RRAM_THROTTLING_DATA_BLOCK which defines the maximum
chunk length that can be written at once.
Add CONFIG_NRF_RRAM_THROTTLING_DELAY which configures the sleep delay in
microseconds after each write.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
The jedec-id cannot be read after flash device is set to octal mode.
Fixed by moving the jedec-id comparison to
flash_flexspi_nor_check_jedec() which already reads the jedec-id when
flash device is still in single spi mode.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Some devices supported by this driver do not have a write-block-size
of 1 such as the mt35xu01gbba. This value is assigned in the dts and can
be used instead.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Fix stm32 XSPI driver to restore the bus command concurrent access
protection that was mistakenly removed on memory mapping operation
by commit e5620e07c9 ("drivers: flash: stm32 xspi flash read with
memcopy when executing").
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This is a follow-up to commit cafa288197.
Bit masks should use the bitwise OR operator, not the logical one...
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
When Octal IO mode is to be used with DDR in mx25u family chips,
bit 1 instead of 0 must be set in the Configuration Register 2 at
address 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
