the option MPU_ALLOW_FLASH_WRITE is only needed
when ARM_MPU. Only files in include/zephyr/arch/arm/mpu/
and include/zephyr/arch/arm64/cortex_r use it. it is not used in
xtensa or riscv.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
as in the spi_nor driver, so that the DPD mode can be used even if
the flash API caller does not perform the runtime device PM calls.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add proper handling of the `has-dpd`, `t-enter-dpd`, and `t-exit-dpd`
devicetree properties that could be applied to "jedec,mspi-nor" nodes,
but caused no effect so far.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Correct alignment of `\` characters in the `FLASH_MSPI_NOR_INST(inst)`
macro definition.
Use `NSEC_PER_USEC` symbols instead of 1000 when doing conversion from
nanoseconds to microseconds.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
A flash manager thread is created and allocated to
process Flash Manager Process.
Definition of KConfigs STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE,
and STM32WBA_FLASH_MNGR_THREAD_PRIO to configure the
flash manager thread.
STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE is setting by default
to 768 bytes. This value was chosen empirically since reasonable
to cover generic cases.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Ready registers are defined for the nrf54h series but not necesssary for
other soc families.
Limit the Ready register check only to this family of socs.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Remove the 'andestech,qspi-nor-xip' compatible string and unify both
flash_andes_qspi.c and flash_andes_qspi_xip.c flash drivers use
'andestech,qspi-nor' compatible string.
The driver selection is now handled via Kconfig logic.
CONFIG_FLASH_ANDES_QSPI_XIP is strickly depends on XIP is enabled and
the 'zephyr,flash' chosen node is compatible with 'andestech,qspi-nor'.
Since these two driver variants cannot coexist, the application is
responsible for enabling the appropriate driver Kconfig.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
When the TimeOut is enabled in MemoryMapped mode, the TO irq callback
has not to give any sem, because the read operation is done with
memcopy(). No sem was taken, nothing to release.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit fixes two boundary calculation bugs within read_non_aligned()
in the nrf_qspi_nor driver:
1. Prefix Alignment: Removed the `if (flash_prefix > size)` check. This
check artificially capped the prefix, resulting in unaligned addresses
being passed to the nrfx HAL.
2. Suffix Out-of-Bounds: Replaced the hardcoded WORD_SIZE * 2 suffix
read with a dynamic size check. Previously, if a read ended near the
physical boundary of the flash chip, the hardcoded 8-byte read would
request memory outside the chip's physical address space.
Fixes#109139Fixes#109140
Signed-off-by: T Madhusudhan Rao <tetakalam@aerlync.com>
memcpy is not optimized for the Cortex-M core due to this :
https://github.com/zephyrproject-rtos/zephyr/issues/95154
Modify this by writing each word individually only when source address
is aligned to 4 bytes boundary.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
When requesting/releasing the no_latency mode for the mram, verify that
the request/release is successful to avoid running into infinite loop if
the mram controller is in autopowerdown mode.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Fix the case where the MRAM writes get corrupted in some conditions.
After each "MRAM_WORD_SIZE write", a read of the written/erased MRAM word
is performed while masking the bus faults to avoid halting the system.
If an error is detected in the BFSR status bits, retry the write for a
maximum of CONFIG_NRF_MRAM_MAX_RETRIES (default 20) times.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
When writes are issued to the mram controller without verifying that it
is ready, it can cause the reads to be stalled until all writes finish.
Fix this by adding a wait busy loop before each MRAM_WORD aligned write
and disable autopowerdown before starting the write.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Add a BULID_ASSERT to make sure that the write_block_size defined in the
device tree is a multiple of the MRAM_WORD_SIZE which is 16B (128 bits)
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Determine the expiry status before the read to ensure that this function
only returns `-ETIMEDOUT`` if the flash still isn't ready *after* the
provided `timeout_us`. Checking after the read (in the while condition)
can result in the status being read once on function entry, then the
thread not resuming from the `k_sleep` until after the timeout expires.
The changes the timeout behaviour of `spi_nand_wait_until_ready` from
"Flash not ready at some point before expiry" to "Flash still not ready
after at least `timeout_us`".
Signed-off-by: Jordan Yates <jordan@embeint.com>
Support setting desiered SPI communication frequency via configuring
the SCLK_DIV divisior in IFTIM register.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
When parts of code are running from EXTXIP and at the same
time QSPI external flash writes/erases are happenning there
is a high risk of a race condition where a thread running
EXTXIP code starts executing while an external flash operation
is in progress; This can lead to execution stalling or
bus faults/usage faults.
The issue was observed when parts of MCUMGR were relocated to
EXTXIP and DFU was performed.
To fix the issue added the CONFIG_NORDIC_QSPI_NOR_XIP_FLASH_SCHED_LOCK
option which should be used when executing parts of code from EXTXIP.
It ensures the blocking variant of nrfx_qspi_ is used and that
no preemption happens while an external flash write is in progress
(by making qspi_wait_while_writing blocking)
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add support for issuing a software reset sequence (RSTEN 0x66 followed
by RST 0x99) to the flash device during initialization, before reading
SFDP parameters.
The feature is controlled by a new devicetree property
'initial-soft-reset'. When enabled, the driver sends the reset
sequence using temporary LUT entries to avoid flash data
access during XIP critical sections.
An optional 't-reset-recovery' property specifies the minimum time in
nanoseconds the flash needs after reset before accepting new commands.
If provided, the driver will busy-wait(self defined) for the
specified duration.
Suggested-by: Sanjay Varghese <Varghesemela@gmail.com>
Link: https://github.com/zephyrproject-rtos/zephyr/pull/105891
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Fix by demoting BIT(6) to a fallback, checked only when no active
entry method bit (BIT(0), BIT(1), BIT(4)) is also set. This aligns
with the approach in Zephyr's generic spi_nor driver and the Linux
kernel spi-nor subsystem, both of which prefer active entry commands
when available and treat the "always 4-byte" indication as a last
resort. Sending 0xB7 to a device that is already in 4-byte mode is
idempotent and harmless.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Edge devices have multiple addresses for the external memory.
SAHB (0x60.., 0x70.. for ns and s access respectively) which
are uncached but programmable and CBUS (0x08.. and 0x18..
for ns and s access respectively) which are cached and improve
performance.
Additionally, cm33 can use both SAHB aliases and CBUS alises
but cm55 can only use SAHB aliases.
Therefore this commit redefines entirely the memory map to
use mapped partitions are offsets from the base region and
selecting the base region accordingly for
the three use cases. (cm33s, cm33ns - for eval board, cm55).
To this selected set USE_DT_CODE_PARTITION
to yes for all cores in defconfig.
Additionally cleaned up config BUILD_OUTPUT_ADJUST_LMA to be
more clear in its use.
Updated the custom linker script with the mapped partitions
updates that were added to the base linker ascript in arm.
Updated the metadata function to handle the addresses
gymnastics.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Introduce Kconfig symbol to add mutex lock protection to the driver API.
Prevent multi-threaded access from a pre-emptive thread.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Set the OSPI memory mapped timeout period to avoid keeping the chip
select line asserted indefinitely after memory mapped accesses.
This is needed when OSPI1 and OSPI2 operate simultaneously with shared
IO0-IO3 and CLK lines, and both instances use memory mapped mode.
The timeout period follows the recommendation from the STM32U575xx and
STM32U585xx device errata, ES0499 section 2.6.4.
Allow dqs-port to be set to 0. The STM32 HAL uses value 0 to indicate
that the DQS port is not used.
Update the debug log printed when CONFIG_STM32_MEMMAP is not enabled,
because stm32_ospi_set_memorymap() is not called in that case.
Signed-off-by: Kirill Shypachov <kshypachov@outlook.com>
Fix the test on the number of arguments in the erase command
to get the optional size argument that was mistakenly increased by
cb2382d25b ("drivers: flash: flash_shell.c: Requires device on
destructive ops") and made the argument never considered.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Even though compat "st,stm32f1-flash-controller" is also used by stm32f0,
stm32f3, stm32l0 and stm32l1 series, these series don't share exactly
the same members of FLASH_TypeDef and OB_TypeDef structures.
For example, the CR member is available on F1 but not on the L0 series.
There is also issue with missing variables or naming conventions :
- FLASH_OBR_RDPRT (F1) vs FLASH_OBR_RDPRT1 (F0)
- RDP_KEY present in F1 series and not in others.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Instead of performing series check, use the new common Kconfig option
CONFIG_HAS_STM32_UNCACHED_ACCESS_ONLY_OTP in drivers which access the
internal NVM's OTP/read-only area.
While at it, use the public `sys_cache_xxx()` API in flash_stm32 instead
of the internal `cache_xxx()` API.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
During read operations, the same buffer was previously used for both TX
and RX, causing arbitrary data from the RX buffer to be transmitted on
MOSI. This could lead to unintended signaling on the bus and unreliable
device behavior, including corrupted reads (e.g. incorrect JEDEC ID).
Fix this by separating TX and RX buffers:
- Do not drive MOSI during read transactions (TX buffer set to NULL)
- Initialize the RX buffer to 0 before use
This ensures clean read operations without spurious data on MOSI.
During SPI operation, the TX buffer supports a maximum length of
6 bytes. It was set to 5 bytes, which could lead to a potential
overflow.
Signed-off-by: Flavien Carvalho <flavien.carvalho@wiifor.com>
When flash_stm32_xspi_init() returns early in the XIP fast path it
leaves layout.pages_size unset. This causes problems for code that
relies on the page layout being available, even in XIP mode. This
commit adds a fallback to ensure a valid page layout is always
available.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Add soc-nv-flash child nodes to the six NXP FlexSPI boards
not yet converted: mimxrt595_evk, mimxrt685_evk, vmu_rt1170
(mx25um51345g), and mimxrt1050_evk, mimxrt1060_evk,
mimxrt1062_fmurt6 (hyperflash).
Update FlexSPI NOR and HyperFlash drivers to read
write_block_size from the soc-nv-flash node. Remove
soc-nv-flash.yaml from hyperflash and mx25um51345g
bindings.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add JEDEC IDs 0x19609D (IS25LP256) and 0x19709D (IS25WP256) to the
IS25 family switch. Like other IS25 variants, dummy cycles are reset
before SFDP probe, which handles the full LUT configuration.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Extend flash and I2C drivers to support BL808 register base addresses
and SoC-specific configuration guards.
Signed-off-by: William Markezana <william.markezana@gmail.com>
While other lines of the STM32 family have their flash controllers with
option bytes driver support, the STM32F1 line was missing it.
(Which might have something to do with the rather complex handling that
it needs to program them.) This patch adds support for modifying the
option bytes as they are represented in FLASH/OBR, which involves erasing
all option bytes (including the write protection bytes), then writing
back the new values for each (restoring the write protection to its
previous value).
Signed-off-by: Benedek Kupper <kupper.benedek@gmail.com>
SF32LB DMA cleared its software busy bit on half-complete.
The QSPI NOR write path polled that bit while holding the flash lock.
Clear the DMA status bit only on completion or error.
Derive busy from the active state plus pending_length.
Poll pending_length until the flash DMA transfer reaches zero.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
The SF32LB MPI QSPI NOR erase path issued WREN only once before
entering the erase loop. On SPI NOR devices the write-enable latch
is typically cleared after each erase command, so a multi-block erase
can fail after the first block.
Move WREN into the loop and issue it while holding the driver lock,
immediately before the selected erase command. This matches the write
path and aligns the driver with Zephyr's generic SPI NOR erase flow.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Initialize the 32-bit DR temporary at declaration before copying a
partial tail chunk in qspi_nor_write_fifo(). Without this, 1-3 byte
writes can leave the upper bytes unchanged and push stale bits into
MPI_DR.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Add support for multiple plane devices to the SPI NAND driver.
This includes adding a new plane-bytes property to the device
tree bindings, which indicates the size of each plane in the
flash device. For devices with a single plane, this should be
set to the same value as size-bytes.
Some devices require the plane address as part of read and/or
program commands. For these devices, the new has-read-plane-select
and has-program-plane-select properties can be set to indicate
that the driver should include the plane address in read and
program commands.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE sets how many line buffers
should be used for the driver. When ther is no need to synchronize
the buffering default value should be maximal
(optimized write performance).
Whe ther is need for synchronize - value should be minimal
buffering - x1 (optimized radio firmware execution).
By mistake the default values were mixed eatch other.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Currently the stm32g4x flash driver only works in dual bank for devices
that support it. This is inconvenient when using mcuboot on a device with
less than the maximum 512k of flash, as it creates an unaddressable "hole"
between the two banks, artificially constraining the partition layout for
the bootloader, primary, and upgrade slots. Update the flash driver to add
a runtime check to see if the device is configured in single bank or dual
bank mode and adjust the page size accordingly. Note that the driver must
do both a compile time and runtime check for dual bank configuration as
dual bank mode is only supported on some devices in the family, and for
those that do support dual bank mode, they may or may not be configured as
such.
Signed-off-by: Michael Estes <michael.estes@byteserv.io>
Add a SPI-NAND flash driver for NXP FlexSPI controller. The driver
probes device geometry (page size, OOB size, pages per block, total
capacity) from the ONFI parameter page at runtime and supports read,
write, and block erase operations. Bad-block detection and marking
are exposed through the flash_ex_op interface, including the
FLASH_EX_OP_IS_BAD_BLOCK and FLASH_EX_OP_MARK_BAD_BLOCK operations.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Add support for the base DT property "supply-gpios" and related
"t-reset-recovery", as in the flash_mspi_nor driver.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fixes zephyrproject-rtos/zephyr#106597
The current driver for the NXP C40 flash controller instantiates two
drivers, one for the controller (which has no real code -- it's just
a device with no API, config, or data), and one for the flash bank.
This breaks the various partition APIs because they expect the flash
driver API to be attached to the "grandparent" of the partitions
object -- but in the current C40 driver, it is attached to the parent.
I was worried this fix was going to be more complicated, but it
appears to have been quite simple. All I needed to do was to
instantiate a single device with the the API, config and data.
The fix requires the "soc-nv-flash" compatibility to be added to
device trees which reference this driver (see previous commit).
This fix addresses the bug report I filed a few days ago:
NXP C40 flash driver incompatibility with partitions macro APIs #106597
Signed-off-by: Rob Newberry <rob@zenomoto.com>
Signed-off-by: rob-zeno <rob@zenomoto.com>
Kinetis ke1xf (twr_ke18f/mke18f16) and k8x (frdm_k82f) select
CONFIG_HAS_MCUX_CACHE but previously fell through to the no-op
clear_flash_caches() path, meaning caches were not invalidated
after flash erase or write operations.
After the FTFE controller completes an erase or write, stale data
may remain in the instruction cache and (on some parts) the system
bus cache. Subsequent reads can return outdated values instead of
updated flash contents. This causes test_flash_erase,
test_flash_fill, and test_flash_flatten in
tests/drivers/flash/common to fail, with data read back as stale
values (e.g. 0xAA from a prior fill).
Rebased on top of #105918 and updated to use Zephyr's generic cache
API (sys_cache_instr_invd_all() / sys_cache_data_invd_all()) for
cache invalidation. This keeps the flash driver SoC-agnostic and
relies on the cache driver (e.g. LMEM) for hardware-specific
handling.
Fixes#98487
Signed-off-by: Mohit Talwar <talwarmohit2005@gmail.com>
NXP FlexSPI NOR flash nodes were missing the soc-nv-flash child
node expected by Zephyr's flash map API.
Without this child node, DT_MTD_FROM_FIXED_PARTITION resolved to
the FlexSPI memory controller instead of the flash device. Since
the controller has api = NULL, MCUboot could hit a NULL pointer
dereference during boot on Zephyr 4.4.
Fix this by updating the DTS structure to match the soc-nv-flash
convention used by the flash map infrastructure.
Changes:
- add a soc-nv-flash child under each nxp,imx-flexspi-nor node
- move erase-block-size, write-block-size, and partitions into it
- add ranges to flash controller nodes for address translation
- update zephyr,flash to point to the soc-nv-flash child
- add zephyr,flash-controller chosen for the flash driver node
- remove soc-nv-flash.yaml from nxp,imx-flexspi-nor.yaml
- use zephyr,flash-controller in flash CMake XIP decisions
- update FlexSPI XIP Kconfig logic to walk to the grandparent
This keeps the controller and flash device roles separate and
restores correct flash map resolution for MCUboot and XIP logic.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
