The GCC 9.2 toolchain for intel_apl_adsp has builtin atomic
functions already so we can use that instead of the custom
one in arch. This allows the atomic function calls to be
inlined.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a rather primitive driver for use with the Intra-DSP
Communication (IDC) on the DSP on certain Intel SoCs. The IDC
generates interrupts from one core to another by writing to
certain registers. This is also being utilized as
the scheduler IPI since it can interrupt other cores.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the DTS binding for the CAVS Intra-DSP Communication (IDC)
driver for the DSP on Intel SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a sys init level which allows device and sys_init
to be done after SMP initialization, z_smp_init(), when all
cores are up and running.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Under multi-processing, only the first CPU#0 needs to go through
setting up the kernel structs and clearing out BSS (among others).
There is no need for other CPUs to do those tasks. Since each
Xtensa core starts using the same boot vector, CPUs other than #0
need to skip all the startup tasks by not calling to z_cstart().
So provide another entry point for those CPUs. Note that Xtensa
arch is highly configurable. So the implementation of the entry
point is up to each individual SoC config.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
EXCSAVE2 is used for level 2 exception save location.
Since we are using level 2 interrupts, use EXCSAVE7
instead as level 7 interrupts are not being used
by the SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer is a timer driven directly by
external oscillator and is external to the CPU core(s).
It provides a common and synchronized counter for all
CPU cores (which is useful for SMP), instead of
indepedently running local core timer (xtensa_timer).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer on some Intel SoC is a timer driven
directly by external oscillator and is external to the CPU
core(s). It is not as fast as the internal core clock, but
provides a common and synchronized counter for all CPU cores
(which is useful for SMP).
This uses the RISCV timer as base as it is using 64-bit
counter.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The CAVS interrupt controller has different base addresses for
each CPU. When running under SMP, the driver needs to look at
the correct address for the CPU the ISR is running so interrupts
can be dispatched correctly. This adds a function to calculate
the correct base address. Note that each supported SoC may have
different offsets so per SoC config will need to added. Support
for intel_s1000 is added as an example.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The dw_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The cavs_ictl interrupt controller is an interrupt aggregator
supporting multi-level interrupts. Therefore, it needs to be
initialized earlier than any downstream interrupt controllers
and devices.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Under SMP, the main BSS section only needs to be zero-ed on CPU #0.
Other CPUs should not zero out BSS, or else it may cause CPU #0 to
crash on invalid data.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adding documentation to inform users that characters may be lost if
polling is used and a character arrives while the system is in standby
mode.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Sleep mode 1 is supposed to be a low-latency sleep mode where devices
are left in active mode. Thus we should only bring devices to low-power
when in sleep mode 2 in sys_pm_policy_low_power_devices().
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
It was observed that leaving the pin type configured for i2c for SDA
and SCL results in higher power consumption during standby. So we are
resetting the pin type when bringing the i2c into low power mode, and
setting it back to the correct type when exiting low power mode.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add a dependency on the I2C resource in the TI Power module,
reconfigure the peripheral upon CPU exiting standby, and add
support for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add a dependency on the UART resource in the TI Power module,
reconfigure the UART upon CPU exiting standby, and add support
for device PM.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Adding a dependency on the GPIO resource in the TI Power module, and
configuring the edge detection on pads as a wakeup source.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
When power management is enabled, SYS_PM_STATE_LOCK is necessary
in order to prevent the power policy from automatically entering
certain sleep states.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Add @stephanosio as a code-owner for the tests/arch/arm
test suites, so they get auto-assigned in reviews.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove a side effect in an assertion check of the
expected reason after spurious interrupt handling.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Fix bug where SHIELDS would be marked as "not found" in the
NOT_FOUND_SHIELD_LIST when they were present, just not in the first
BOARD root in the BOARD_ROOT list.
Instead of marking shields in the NOT_FOUND_SHIELD_LIST, we (continue)
popping shields from SHIELD and check if there are any shields left in
SHIELD.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The board porting guide now has useful information on supporting
flash/debug commands. Link to it from the top of the page describing
these commands to hopefully make it easier to find.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Originally reported in #23539 (though that seems to have been another
problem), west flash and friends are dumping stack when used with an
unconfigured runner.
Let's just promote the warning about this to an error. The idea that
this ever could have worked without explicit support has not worked
out in practice, to my knowledge.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Don't generate a Z_OOPS() if k_thread_abort() is called on a
thread that isn't running. Just return to the caller instead,
much like how k_thread_join() functions.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
z_vrfy_counter_get_value should check the size of memory pointed to
ticks and not the size of the pointer.
Fixes: #22431
Coverity CID :207984
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
gpio_pin_get() returns a negative value in case of error and
callbacks_configure was assigning this value to an unsigned variable.
Fixes: #22643
Coverity CID :208206
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit changes the behaviour of the CMSIS-RTOS periodic timers to
have an initial timeout equal to the periodic timeout instead of
executing the callback function directly when calling the
osTimerStart(...); function.
This behavioural change is according to the CMSIS-RTOS specification.
Signed-off-by: Måns Ansgariusson <Mans.Ansgariusson@AssaAbloy.com>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
These are short-circuiting utility helpers that can save typing
in situations where avoiding evaluation of the not-taken branch
skips invalid expressions.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In case OPENTHREAD_NCP option is disabled, uart.c platform driver should
not be compiled as it misses dependencies.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Introduce an update in the mbedTLS configuration, which is needed after
the OpenThread update. The default mbedTLS CMake configuration was
changed upstream, which resulted in broken cryptography in Zephyr.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
This was a simple missing macro, that prevented flash_shell to build
for stm32f4 based boards (which is weird, CI should have caught that
much earlier)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
In addition to the existing plain TCP MQTT test, add the same test
with TLS applied. Robert Lubos provided the updated test_cert.h, which
contains the same certificate as in the echo samples.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
OpenThread NCP sample application.
Tested on FRDM-K64 with RF2XX connected via USB to a Linux machine
running wpantund.
Signed-off-by: Markus Becker <markus.becker@tridonic.com>
When NCP starts-up some of the initialisation functions of a regular
OpenThread device do not need to be called, because they get triggered
by wpantund via UART. Instead NCP initialisation needs to be called.
A small typo has been fixed as well.
Also initialisation for raw link packet interface has been added. Can be
used for picking up 802.15.4 frames and interpreting them in the
application.
Signed-off-by: Markus Becker <markus.becker@tridonic.com>
