Print just the basename of the Input and Output filenames
when creating the board specific image for Intel S1000 CRB
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Be consistent in how board docs are named and move all to index.rst.
This will make the URL to the board documentation predictable and easier
to remember.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The phrase "Zephyr applications use the ..." in many boards and
inconsistently. This is just to say what is the board identify is.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Somehow these were getting generated as `FLASH_foo_BLOCK_SIZE` even
though there's no specification for them in the original yaml. Put them
back until we can figure out what's going on.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Now that all supported xtensa boards use DTS we can move the Kconfig
setting to the arch level. Remove HAS_DTS from board Kconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change compatible, move the JEDEC ID from Kconfig to DTS, convert DTS
size from bytes to bits, remove unreferenced DTS properties. Remove DTS
fixups.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This patchset introduces support for building a board specific custom
image for intel_s1000_crb. This pads the output binary (zephyr.bin)
with some additional data as required by the s1000 BootROM.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Fix the following dtc warnings on S1000:
Warning (simple_bus_reg): /soc/pinmux@81C30: simple-bus unit
address format error, expected "81c30"
Warning (alias_paths): /aliases: aliases property name must
include only lowercase and '-'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some extensions to the multi-level interrupt controller are required
to support SoCs with more than four level 2 interrupt "aggregators".
Extend existing support to allow at most 8 level 2 or level 3
aggregators. Use Kconfig macro templates to cut down on boilerplate.
Try to clarify some aspects of the Kconfig help while we're at it, and
change the type of options which count things or are table offsets
from "hex" to "int", so that the generated .config is easier to read.
Finally, make some improvements to gen_isr_tables.py while we are
here. In particular, move some assignments around to cut down on
duplicated work, don't check for symbols we know must exist, and
improve the debug logging output's readability.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Configuration of Erase command is specified in DTS. Hence
the corresponding changes in Kconfig are removed.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Number of sectors is now calculated from the flash density
i.e. (Flash size)/(sector size).
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
FIFO_DEPTH should be in the SoC's Kconfig as this is a
configuration of SPI master controller in SoC.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This patchset introduces partitioning of flash in terms of blocks
(flash page layout) for s1000. This partitioning is currently to
be used for mcubootloader.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Use DT_ instead of CONFIG_ for spi freq, spi bus name, flash device
name and flash base address.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Provide a dtsi file that sets up common capabilities for all
Feather-based Particle Mesh devices. Provide additional dtsi files for
some obvious peripheral options.
Remove the xtensa esp32 image: it didn't build, and there's no
indication of how the ESP32 firmware can be updated on the Argon board.
Use particle_argon as the nRF52840 side of the board.
Add Particle Boron support.
Note that dtsi files must be replicated in each board directory until
tooling supports DTS includes from a shared area.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add the codec reset GPIO to intel_s1000_crb's DTS
Update the DTS fixup for intel_s1000_crb accordingly
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
patch set the config USB_DFU_MAX_XFER_SIZE to 4096. This will
reduce the time required for flashing.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Removed Console dependencies from shell uart backend.
Generated define: CONFIG_UART_SHELL_ON_DEV_NAME for each board.
Fixes#10191
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
CONFIG_TEXT_SECTION_OFFSET allows the entire image to be moved
in memory to allow space for some type of header. The mcubootloader
can boot only such images which reserve some space for the header.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This can help find unused symbols. Those end up without a type if
'default' is used instead of 'def_bool', which generates a warning.
Search for "Kconfig.defconfig" in
https://docs.zephyrproject.org/latest/application/kconfig-tips.html for
a longer explanation.
Keep the 'def_bool' for the following symbols, which seem to be
deliberately defined only in Kconfig.defconfig files:
- ALTERA_AVALON_I2C
- ALTERA_AVALON_MSGDMA
- ALTERA_AVALON_PIO
- ALTERA_AVALON_QSPI
- ALTERA_AVALON_SYSID
- CLOCK_CONTROL_IMX_CCM
- CPU_EM4_DMIPS
- CPU_EM4_FPUDA
- CPU_EM4_FPUS
- FP_FPU_DA
- I2C_GECKO
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Turning 'def_bool' in Kconfig.defconfig files into 'default' revealed
three unused symbols (confirmed with 'git grep'). Remove them.
Search for "Kconfig.defconfig" in
https://docs.zephyrproject.org/latest/application/kconfig-tips.html for
an explanation of how def_bool->default can reveal undefined symbols.
Removed unused symbols:
- SPI_DW_CLOCK_GATE
- PINMUX_MPS2
- BOARD_XTENSA
Also remove an assignment to the promptless symbol ALTERA_AVALON_SYSID,
in tests/boards/altera_max10/sysid/prj.conf. Assignments to promptless
symbols have no effect.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Application should be responsible for enabling various drivers and
features, we should not enable everything by default.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds the necessary bits to support ASM2 with XCC
for Intel S1000 SoC. With ASM2 enabled, xcc is now
required to build for Intel S1000 SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr configuration system uses many different files in many
different formats. It makes it a lot easier for users to understand
what these files do if when we use the correct file extensions.
To this end we rename the dts.fixup files to the correct file
extension '.h'.
This is a breaking change for out-of-tree fixup files. Such files will
be detected and given an appropriate error message.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The i2c drivers now consistently select HAS_DTS_I2C, so we no longer
need to select it at the board level.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added an entry in drivers/Kconfig for audio
Added an entry in drivers/audio/Kconfig for audio codec
Added an Kconfig file in drivers/audio/ for TLV320DAC
Enabled audio coded in Intel S1000 CRB defconfig
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
The file boards/common/intel_s1000_crb.board.cmake is not common at
all; it is specific to this board. Move its contents into the board's
board.cmake.
Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The Kconfig option TOOLCHAIN_VARIANT (not to be confused with
ZEPHYR_TOOLCHAIN_VARIANT) is a legacy configuration option that has
very few use-cases and can easily be dropped.
It's functionality is easily covered by CONFIG_X86_IAMCU and
ZEPHYR_TOOLCHAIN_VARIANT.
This commit removes all references of it from Zephyr.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add support to enable test application selectively based
on defconfig
Change-Id: I8111750ff099edd95ffa22c6e312999c801678ea
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A brief description about intel_s1000 and ways to connect,
flash, debug etc.
Change-Id: I459c64d8d9574bc3511da7f983d68e044cacc1d0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS I2S on intel_s1000. Also, introduce a test to
validate I2S in ping-pong and normal modes.
Change-Id: Iea78e22cedc7724c1c2e821c68d7030cc0a65047
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.
Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset creates Debug, Debugserver and Flash scripts
ensuring support in the ZephyrBinaryRunner mode.
Change-Id: Ib4f7820b1c6a045bd67cf4a031be99cf61e65eca
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.
Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 makes use of DesignWare IP for I2C.
Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.
Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.
Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).
Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We want to support other toolchain not based on GCC, so the variable is
confusing, use ZEPHYR_TOOLCHAIN_VARIANT instead.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some boards are supported natively by qemu. This option will allow us to
run tests using those platforms directly without having to go via a
dedicated qemu board definition.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to be able to document the build on Windows and UNIX
systems, slight variations are required on the app commands
that are used throughout the documentation system.
This includes getting rid of the prompt symbol and providing commands
for both UNIX and Windows operating systems.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.
Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Update board definitions with supported feature. This is temporary
until we have full coverage for device drivers in DTS, then we can use
DTS instead.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The various runners (flash/debug scripts) use environment variables to
take arguments. This is legacy behavior which is not desirable.
Use command line arguments instead.
Note: this leaves more general environment variables with publicly
documented behavior in place for now, for compatibility, e.g.:
ZEPHYR_FLASH_OVER_DFU, OPENSDA_FW, ESP_IDF_PATH, PYOCD_DAPARG
For example, when using dfu-util to flash arduino_101, instead of
setting DFUUTIL_PID, DFUUTIL_ALT, and DFUUTIL_IMG environment
variables, have the script invocation look like this:
python3 .../zephyr_flash_debug.py dfu-util flash \
[common arguments omitted] \
--pid=8087:0aba --alt=x86_app \
--img=.../build/zephyr/zephyr.bin
Make similar changes for other runners (openocd, etc.) and
targets (debug, debugserver).
To implement this in the scripts:
- have the individual scripts/support/runner/some-runner.py files
register their own command line arguments
- teach them to construct instances from arguments, not the
environment
- have zephyr_flash_debug.py request runners to register command
line argument parsers, and handle arguments
In the build system:
- add a new board_runner_args() extension function that board.cmake
files can use to add to the zephyr_flash_debug.py command line
- adjust cmake/flash/CMakeLists.txt to invoke with arguments
- add new helper include files for each runner (like
boards/common/dfu-util.board.cmake, etc.), which add default
options as needed and then add on overrides from
board_runner_args() calls
- update board.cmake files to use the new includes and extension
This implied some tweaking when using openocd to make the CMake string
escaping and unescaping work properly.
Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
The Python-based runners have replaced the old shell scripts. Refactor
the build system accordingly:
- FLASH_SCRIPT is now BOARD_FLASH_RUNNER
- DEBUG_SCRIPT is now BOARD_DEBUG_RUNNER
The values, rather than being the names of files, are now the names of
runners in scripts/support/runner. They are still short, descriptive
names like "openocd", "jlink", "em-starterkit", etc.
Adjust the zephyr_flash_debug.py call and runner internals
accordingly. Have each runner class report a name and the commands it
can handle. This lets us move some boilerplate from each do_run()
method into the common run() routine, and enables further improvements
in future patches.
The handles_command() method is temporary, and will be replaced by a
more general mechanism for describing runner capabilities in a
subsequent patch. The initial use case for extending this is to add
device tree awareness to the runners.
To try to avoid user confusion, abort the configuration if an
xxx_SCRIPT is defined.
Signed-off-by: Marti Bolivar <marti@opensourcefoundries.com>
Footnote reference in a code block is ignored. This text shouldn't
really be in a code block anyway, so just make it a paragraph with a
trailing footnote reference.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Not all boards require the various binary formats zephyr generates. So
be selective based on the arch, SoC or board and only geenrate the
binaries actually needed.
Fixes#5009
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
This should clear up some of the confusion with random number
generators and drivers that obtain entropy from the hardware. Also,
many hardware number generators have limited bandwidth, so it's natural
for their output to be only used for seeding a random number generator.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Clean up & rework JTAG documentation for ESP-32 boards to provide full
commands and clarify gotchas.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Supports both master and slave mode, standard and fast modes,
configurable timeouts, and a few other tunable settings.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
ESP-IDF is in constant development and it's likely that files Zephyr
depends on will be moved, removed, or renamed. Make a note that an
older version of ESP-IDF should be used instead.
Closes#1538.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Move all QEMU related defines to the boards and cleanup xtensa platforms
which were marked to be QEMU capable by mistake.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
xtensa uses more stack than other arches, enable the sentinel since we
don't currently have HW-assisted stack checking on this arch.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ESP-WROOM-32 board exits the bootloader at 40 MHz, not 160 MHz as
suggested by documentation. The CCOUNT special register works as
advertised, but not at the expected rate. This was verified by
timestamping (at the host) the output of a dependency-free loop that
looks like:
int key = irq_lock();
while(1) {
u32_t i, count;
volatile int dummy;
for(i = 0; i < 5000000; i++) {
dummy++;
}
__asm__ volatile ("rsr.ccount %0" : "=a"(count));
printk("%d\n", count);
}
The SoC has a fairly robust set of possible CPU clocking modes, but we
don't have a driver for that yet. Until we do, set the single
configured CPU frequency to the one we get at runtime.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr. Some things are still
unconverted, mainly the exception table, and this will be performed
another time.
Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The random number generator from ESP32 uses noise from Wi-Fi and
Bluetooth radios. If these are off, a pseudo-random number is
generated instead; this is currently the case, but even though it's a
black box, it's arguably better than returning a timestamp as a
pseudo-random number generator.
According to the ESP32 Technical Reference manual, the RNG passed the
Dieharder Random Number Test suite (version 3.31.1)[1], but nothing has
been said about the quality of the PRNG.
The RNG register is read directly; no effort is made to use its
contents to feed an entropy pool in a way that's similar to /dev/random
on POSIX systems, as no such subsystem exists on Zephyr at the moment.
[1] http://webhome.phy.duke.edu/~rgb/General/dieharder.php
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This provides basic GPIO support, with interrupts, and the ability to
read and write to ports on a pin-by-pin basis.
Jira: ZEP-2286
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This implements a driver for the pin multiplexer as present in the ESP32
SoCs.
All APIs are supported.
Jira: ZEP-2297
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
ReST defines interpreted text roles where text enclosed by single quotes
can be "intrepreted", for example :ref:`some name` becomes a link to
a label anywhere in the doc set named "some name", :c:func:`funcname()`
becomes a link to the API documentation for "funcname", and
:option:`CONFIG_NAME` becomes a link to, in our case, the documentation
for the generated Kconfig option.
This patch fixes uses of `some name` (without a role) by either adding
an explicit role, or changing to ``some name``, which indicates inline
code block formatting (most likely what was intended).
This is a precursor to changing the default behavior of interpreted
text to treat `some name` as :any:`some name` (as configured in
doc/conf.py), which would attempt to create a link to any available
definition of "some name".
We may not change this default role behavior, but it becomes an option
after the fixes in this patch. In any case, this patch fixes incorrect
uses of single-quoted text (possibly introduced because GitHub's
markdown language uses single-quoted text for inline code formatting).
Jira: ZEP-2414
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The documentation details how to install and configure all the
pre-requisites to build Zephyr for the ESP32 SoC, including using the
vendor SDK and toolchain, the flashing tool, and how to use JTAG.
Jira: ZEP-2109
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This will allow checking if we are building for QEMU globally, without
having to know the exact architecture and board name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Sidebar navigation for supported boards is wonky: opens to show
all boards (making for lots of scrolling to see the sidebar) and
sidebar items aren't always clickable (as explained in the JIRA
issue).
Fix is to not use multiple toctree directives in boards.rst and
create intermediate architecture-specific supported board docs.
JIRA: INF-132
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add board metadata to be consumed by the sanitycheck script to provide
better matching with testcases and to test based on features declated in
the board files.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This flashes Zephyr at 0x1000: that's where the first stage bootloader,
part of the ESP32 ROM, expects to find an "image header".
The second-stage bootloader, part of ESP-IDF, isn't used by the Zephyr
port. However, the bootloader can be used if desired; please refer to
the ESP-IDF documentation on how to set up partitions tables and use
the bootloader.
The following environment variables will affect the ESP32 flashing
process:
Variable Default value
ESP_DEVICE /dev/ttyUSB0
ESP_BAUD_RATE 921600
ESP_FLASH_SIZE detect
ESP_FLASH_FREQ 40m
ESP_FLASH_MODE dio
ESP_TOOL espidf
It's impossible to determine which serial port the ESP32 board is
connected to, as it uses a generic RS232-USB converter. The default of
/dev/ttyUSB0 is provided as that's often the assigned name on a Linux
machine without any other such converters.
The baud rate of 921600bps is recommended. If experiencing issues when
flashing, try halving the value a few times (460800, 230400, 115200,
etc). It might be necessary to change the flash frequency or the flash
mode; please refer to the esptool documentation for guidance on these
settings.
If ${ESP_TOOL} is set to "espidf", the esptool.py script found within
ESP-IDF will be used. Otherwise, this variable is handled as a path to
the tool.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs. So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.
This ESP32-specific initialization will perform the following:
- Disable the watchdog timer that's enabled by the bootloader
- Move exception handlers to IRAM
- Disable normal interrupts
- Disable the second CPU
- Zero out the BSS segment
Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Unconditionally use CONFIG_SIMULATOR_XTENSA to determine if XT_SIMULATOR
or XT_BOARD should be defined.
If CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, also define XT_CLOCK_FREQ. This
isn't ideal as the clock frequency might be changed in runtime and this
effectively makes it a constant.
Until we can control the clock frequency in runtime, this will suffice.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This is a minimal driver enabling console output during the port
bringup. While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts. This will most likely be superceded by a proper
driver after the port has matured.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Now that we can specify what toolchain is intended for each
SOC, enable some more SOCs to be built.
A full sanitycheck run will require the installation of both
RF-2016.4 and RG-2016.4 releases.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The xtensa simulator can in fact simulate a variety of Xtensa SOCs.
Fixes build for alternate xt-sim_* defconfigs.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The xt-sim defconfigs were selecting CONFIG_SIMULATOR_XTENSA instead
of CONFIG_BOARD_SIMULATOR_XTENSA.
Fix defconfigs and rename to CONFIG_BOARD_XT_SIM to ease any future
confusion between these similarly named defconfigs.
CONFIG_SIMULATOR_XTENSA is automatically set by xt-sim's
Kconfig.defconfig, it doesn't need to be explicitly specified in the
defconfigs themselves.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This core configuration was removed from the tree since it cannot
implement irq_offload().
Remove an orphaned block in xtesna.ini.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
More general spelling fixes, and cleaning up stray UTF-8 characters
such as curly-quotes, em- and en-dashes. Use replacement strings
for |reg| and |trade|.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The core build in the SDK does not have a timer, making it impossible
to use this core with most of the sanity checks. We are working on
getting a special package of cores for Zephyr which meet our build
requirments; until then, remove this core as it doesn't build.
Change-Id: I3fa201f3c6b5724501e8cb1e1b8ba631436ebc23
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
* CONFIG_SOC is now properly set and we do not need a separate
XTENSA_CORE build variable
* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed
* There is no default SOC selection, it is now done explicitly in
the board's defconfig
* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
uppercase> to conform to established style.
Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Master branch changed requirements for license headers while this
branch has been in development.
Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This platform is not a real board but let user handle the xtensa
simulator just like a board.
This is needed until a qemu like simulaotr is added to Xtensa.
Change-Id: I54ab28e86eea956cf85af3ee9b4a10f0d531e54d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
