xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate XTENSA_CORE build variable * Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed * There is no default SOC selection, it is now done explicitly in the board's defconfig * CONFIG_<board name> now renamed to CONFIG_SOC_<board name in uppercase> to conform to established style. Issue: ZEP-1711 Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
parent
deea71b3c6
commit
11ee791b32
33 changed files with 188 additions and 77 deletions
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@ -5,10 +5,8 @@
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choice
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prompt "XTENSA core Selection"
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default sample_controller
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depends on XTENSA
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source "arch/xtensa/soc/Kconfig.cores"
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source "arch/xtensa/soc/*/Kconfig.soc"
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endchoice
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menu "XTENSA Options"
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@ -1,5 +1,3 @@
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SOC_PATH=${XTENSA_CORE}
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export SOC_PATH
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flagBoardType=
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ifeq ($(CONFIG_BOARD_XTENSA),y)
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@ -20,9 +18,7 @@ KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) \
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$(call cc-option,-fdata-sections,)
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KBUILD_AFLAGS += $(flagBoardType)
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KBUILD_CFLAGS += -DPROC_$(XTENSA_CORE) \
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-DCONFIG_$(XTENSA_CORE) \
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$(flagBoardType) \
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KBUILD_CFLAGS += $(flagBoardType) \
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$(call cc-option,-fms-extensions,)
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include $(srctree)/arch/$(ARCH)/core/Makefile
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if D_233L
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if SOC_D_108MINI
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config SOC
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string
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default D_108mini
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config IRQ_OFFLOAD_INTNUM
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default 7
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6
arch/xtensa/soc/D_108mini/Kconfig.soc
Normal file
6
arch/xtensa/soc/D_108mini/Kconfig.soc
Normal file
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@ -0,0 +1,6 @@
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_D_108MINI
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bool "D_108mini core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if D_212GP
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if SOC_D_212GP
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config SOC
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string
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default D_212GP
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config IRQ_OFFLOAD_INTNUM
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default 7
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6
arch/xtensa/soc/D_212GP/Kconfig.soc
Normal file
6
arch/xtensa/soc/D_212GP/Kconfig.soc
Normal file
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@ -0,0 +1,6 @@
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_D_212GP
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bool "D_212GP core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if D_108mini
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if SOC_D_233L
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config SOC
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string
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default D_233L
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config IRQ_OFFLOAD_INTNUM
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default 7
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6
arch/xtensa/soc/D_233L/Kconfig.soc
Normal file
6
arch/xtensa/soc/D_233L/Kconfig.soc
Normal file
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@ -0,0 +1,6 @@
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_D_233L
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bool "D_233L core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if XRC_D2PM
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if SOC_XRC_D2PM
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config SOC
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string
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default XRC_D2PM
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config IRQ_OFFLOAD_INTNUM
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default 11
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6
arch/xtensa/soc/XRC_D2PM/Kconfig.soc
Normal file
6
arch/xtensa/soc/XRC_D2PM/Kconfig.soc
Normal file
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@ -0,0 +1,6 @@
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XRC_D2PM
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bool "XRC_D2PM core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if XRC_D2PM_5swIrq
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if SOC_XRC_D2PM_5SWIRQ
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config SOC
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string
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default XRC_D2PM_5swIrq
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config IRQ_OFFLOAD_INTNUM
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default 22
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6
arch/xtensa/soc/XRC_D2PM_5swIrq/Kconfig.soc
Normal file
6
arch/xtensa/soc/XRC_D2PM_5swIrq/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XRC_D2PM_5SWIRQ
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bool "XRC_D2PM_5swIrq (XRC_D2PM core with 4 additional SW IRQs)"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi_mini
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if SOC_XRC_FUSION_AON_ALL_LM
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config SOC
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string
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default XRC_FUSION_AON_ALL_LM
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config IRQ_OFFLOAD_INTNUM
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default 13
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6
arch/xtensa/soc/XRC_FUSION_AON_ALL_LM/Kconfig.soc
Normal file
6
arch/xtensa/soc/XRC_FUSION_AON_ALL_LM/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XRC_FUSION_AON_ALL_LM
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bool "XRC_FUSION_AON_ALL_LM core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi2_std
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if SOC_HIFI2_STD
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config SOC
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string
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default hifi2_std
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config IRQ_OFFLOAD_INTNUM
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default 7
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6
arch/xtensa/soc/hifi2_std/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi2_std/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI2_STD
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bool "hifi2_std core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if XRC_FUSION_AON_ALL_LM
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if SOC_HIFI3_BD5
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config SOC
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string
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default hifi3_bd5
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config IRQ_OFFLOAD_INTNUM
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default 13
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6
arch/xtensa/soc/hifi3_bd5/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi3_bd5/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI3_BD5
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bool "hifi3_bd5 core"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi3_bd5_call0
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if SOC_HIFI3_BD5_CALL0
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config SOC
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string
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default hifi3_bd5_call0
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config IRQ_OFFLOAD_INTNUM
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default 13
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6
arch/xtensa/soc/hifi3_bd5_call0/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi3_bd5_call0/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI3_BD5_CALL0
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bool "hifi3_bd5_call0 (hifi3_bd5 core with call0 ABI and 3 additional SW IRQs)"
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@ -4,7 +4,11 @@
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi4_bd7
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if SOC_HIFI4_BD7
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config SOC
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string
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default hifi4_bd7
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config IRQ_OFFLOAD_INTNUM
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default 4
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6
arch/xtensa/soc/hifi4_bd7/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi4_bd7/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI4_BD7
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bool "hifi4_bd7 core"
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi3_bd5
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if SOC_HIFI_MINI
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config SOC
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string
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default hifi_mini
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config IRQ_OFFLOAD_INTNUM
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default 13
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6
arch/xtensa/soc/hifi_mini/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi_mini/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI_MINI
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bool "hifi_mini core"
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if hifi_mini_4swIrq
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if SOC_HIFI_MINI_4SWIRQ
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config SOC
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string
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default hifi_mini_4swIrq
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config IRQ_OFFLOAD_INTNUM
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default 1
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6
arch/xtensa/soc/hifi_mini_4swIrq/Kconfig.soc
Normal file
6
arch/xtensa/soc/hifi_mini_4swIrq/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_HIFI_MINI_4SWIRQ
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bool "hifi_mini_4swIrq (hifi_mini core with 4 additional SW IRQs)"
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@ -1,12 +0,0 @@
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# Kconfig - XTENSA board configuration
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if sample_controller
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config IRQ_OFFLOAD_INTNUM
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default 7
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endif
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16
arch/xtensa/soc/sample_controller/Kconfig.defconfig
Normal file
16
arch/xtensa/soc/sample_controller/Kconfig.defconfig
Normal file
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# Kconfig - XTENSA board configuration
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SAMPLE_CONTROLLER
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config SOC
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string
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default sample_controller
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config IRQ_OFFLOAD_INTNUM
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default 7
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endif
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6
arch/xtensa/soc/sample_controller/Kconfig.soc
Normal file
6
arch/xtensa/soc/sample_controller/Kconfig.soc
Normal file
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SAMPLE_CONTROLLER
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bool "sample_controller core"
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_IPM_CONSOLE_STACK_SIZE=2048
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CONFIG_XTENSA=y
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CONFIG_SOC_SAMPLE_CONTROLLER=y
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CONFIG_SIMULATOR_XTENSA=y
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CONFIG_CONSOLE=y
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XTENSA_ISS_CYCLES_LIMIT=1000000000 # Simulate 10^9 cycles.
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XTENSA_ISS_CYCLES_LIMIT := 1000000000 # Simulate 10^9 cycles.
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ifndef XTENSA_TOOLS_PATH
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$(error Please set XTENSA_TOOLS_PATH first)
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$(error Please set XTENSA_TOOLS_PATH first)
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endif
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ifndef XTENSA_BUILDS_PATH
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$(error Please set XTENSA_BUILDS_PATH first)
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$(error Please set XTENSA_BUILDS_PATH first)
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endif
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XTENSA_BUILD_DIR:=$(patsubst "%",%,${XTENSA_BUILD_DIR})
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XTENSA_BUILD_DIR := $(patsubst "%",%,${XTENSA_BUILD_DIR})
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ifeq (${XTENSA_BUILD_DIR},)
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XTENSA_BUILD=$(shell echo ${XTENSA_BUILDS_PATH}/${XTENSA_CORE})
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XTENSA_BUILD=$(shell echo ${XTENSA_BUILDS_PATH}/${CONFIG_SOC})
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else
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ifeq ($(patsubst /%,/,${XTENSA_BUILD_DIR}),/)
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XTENSA_BUILD=${XTENSA_BUILD_DIR}
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else
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XTENSA_BUILD=$(shell echo ${CONFIG_XTENSA_BUILDS_PATH}/${XTENSA_BUILD_DIR})
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endif
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ifeq ($(patsubst /%,/,${XTENSA_BUILD_DIR}),/)
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XTENSA_BUILD=${XTENSA_BUILD_DIR}
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else
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XTENSA_BUILD=$(shell echo ${CONFIG_XTENSA_BUILDS_PATH}/${XTENSA_BUILD_DIR})
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endif
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endif
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# Strip quotes from cross compiler anme prefix
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CROSS_COMPILE_xtensa=$(patsubst "%",%,${CONFIG_CROSS_COMPILE})
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ifeq (${CROSS_COMPILE_xtensa},)
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# Use default name prefix if no cross compiler name prefix is set
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CROSS_COMPILE_xtensa=xt-
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# Use default name prefix if no cross compiler name prefix is set
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CROSS_COMPILE_xtensa=xt-
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endif
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ifeq (${CONFIG_XTENSA},y)
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CROSS_COMPILE=${XTENSA_TOOLS_PATH}/bin/$(CROSS_COMPILE_$(ARCH))
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CROSS_COMPILE = ${XTENSA_TOOLS_PATH}/bin/$(CROSS_COMPILE_$(ARCH))
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ifeq ($(USE_CCACHE),1)
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CC=$(CCACHE) ${CROSS_COMPILE}xcc --xtensa-core=$(XTENSA_CORE)
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CXX=$(CCACHE) ${CROSS_COMPILE}xc++ --xtensa-core=$(XTENSA_CORE)
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CC = $(CCACHE) ${CROSS_COMPILE}xcc --xtensa-core=$(CONFIG_SOC)
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CXX = $(CCACHE) ${CROSS_COMPILE}xc++ --xtensa-core=$(CONFIG_SOC)
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else
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CC=${CROSS_COMPILE}xcc --xtensa-core=$(XTENSA_CORE)
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CXX=${CROSS_COMPILE}xc++ --xtensa-core=$(XTENSA_CORE)
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CC = ${CROSS_COMPILE}xcc --xtensa-core=$(CONFIG_SOC)
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CXX = ${CROSS_COMPILE}xc++ --xtensa-core=$(CONFIG_SOC)
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endif
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AS=${CROSS_COMPILE}as --xtensa-core=$(XTENSA_CORE)
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LD=${CROSS_COMPILE}ld --xtensa-core=$(XTENSA_CORE)
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AS = ${CROSS_COMPILE}as --xtensa-core=$(CONFIG_SOC)
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LD = ${CROSS_COMPILE}ld --xtensa-core=$(CONFIG_SOC)
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CROSS_COMPILE_TARGET = ${CROSS_COMPILE_TARGET_${ARCH}}
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#CORES
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XTENSA_CORES_LIST=$(shell sed -ne 's/^config \(.*\)/\1 /p' \
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${ZEPHYR_BASE}/arch/xtensa/soc/Kconfig.cores)
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define XTENSA_CORE_CHECK
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ifeq ($$(CONFIG_$(strip $1)),y)
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XTENSA_CORE=$(strip $1)
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endif
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endef
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define XTENSA_CORES_CHECK
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$(foreach core,${XTENSA_CORES_LIST}, $(call XTENSA_CORE_CHECK, ${core}))
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endef
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$(eval ${XTENSA_CORES_CHECK})
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ifeq (${XTENSA_CORE},)
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$(error Failed to parse "arch/xtensa/soc/Kconfig.cores" for getting cores list)
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endif
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XTENSA_SYSTEM=$(XTENSA_BUILD)/config
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XTSC_INC=$(realpath $(patsubst "%",%,${CONFIG_XTENSA_XTSC_INC}))
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@ -93,8 +79,8 @@ KBUILD_CXXFLAGS:=$(filter-out \
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XTRUN=${CROSS_COMPILE}run
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XTRUN_FLAGS += --cycle_limit=${XTENSA_ISS_CYCLES_LIMIT}
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export CROSS_COMPILE XTENSA_CORE XTENSA_SYSTEM LIB_INCLUDE_DIR
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endif
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export CROSS_COMPILE XTENSA_SYSTEM LIB_INCLUDE_DIR
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endif # CONFIG_XTENSA
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prepare2:
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${Q}test -d ${XTENSA_BUILD} || ( \
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@ -10,9 +10,9 @@ ifneq (${QEMU_PTY},)
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endif
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run: zephyr
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@echo "**** Running simulation for Xtensa core \"${XTENSA_CORE}\" ****"
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@echo "**** Running simulation for Xtensa core \"${CONFIG_SOC}\" ****"
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$(if ${QEMU_PIPE},,@echo "To exit from XT-RUN enter: 'CTRL+c'")
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@echo '[XT-RUN] CPU: ${XTENSA_CORE}'
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@echo '[XT-RUN] CPU: ${CONFIG_SOC}'
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# Run the emulator in the background and leave a PID file for
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# sanitycheck
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ifneq ($(QEMU_PIPE),)
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xtsc-run:run
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run:zephyr
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${Q}echo "***** Running simulation for Xtensa core \"${XTENSA_CORE}\" *****"
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||||
${Q}echo "***** Running simulation for Xtensa core \"${CONFIG_SOC}\" *****"
|
||||
$(if ${QEMU_PIPE},,@echo "To exit from XTSC-RUN enter: 'CTRL+c'")
|
||||
@echo '[XTSC-RUN] CPU: ${XTENSA_CORE}'
|
||||
@echo '[XTSC-RUN] CPU: ${CONFIG_SOC}'
|
||||
${Q}test -f ${XTSC_INC} || ( \
|
||||
echo '*** Error: $@ requires valid XTSC include file in \
|
||||
"$${CONFIG_XTENSA_XTSC_INC}"' && \
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue