xtensa: build similar to other Zephyr arches

* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

arch/xtensa/Kconfig

@@ -5,10 +5,8 @@
 
 choice
 	prompt "XTENSA core Selection"
-	default sample_controller
 	depends on XTENSA
-
-source "arch/xtensa/soc/Kconfig.cores"
+	source "arch/xtensa/soc/*/Kconfig.soc"
 endchoice
 
 menu "XTENSA Options"

arch/xtensa/Makefile

@@ -1,5 +1,3 @@
-SOC_PATH=${XTENSA_CORE}
-export SOC_PATH
 
 flagBoardType=
 ifeq ($(CONFIG_BOARD_XTENSA),y)
@@ -20,9 +18,7 @@ KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) \
 		 $(call cc-option,-fdata-sections,)
 
 KBUILD_AFLAGS += $(flagBoardType)
-KBUILD_CFLAGS += -DPROC_$(XTENSA_CORE) \
-		 -DCONFIG_$(XTENSA_CORE) \
-		 $(flagBoardType) \
+KBUILD_CFLAGS += $(flagBoardType) \
 		 $(call cc-option,-fms-extensions,)
 
 include $(srctree)/arch/$(ARCH)/core/Makefile

arch/xtensa/soc/D_108mini/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if D_233L
+if SOC_D_108MINI
+
+config SOC
+	string
+	default D_108mini
 
 config IRQ_OFFLOAD_INTNUM
 	default 7

arch/xtensa/soc/D_108mini/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_D_108MINI
+	bool "D_108mini core"
+

arch/xtensa/soc/D_212GP/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if D_212GP
+if SOC_D_212GP
+
+config SOC
+	string
+	default D_212GP
 
 config IRQ_OFFLOAD_INTNUM
 	default 7

arch/xtensa/soc/D_212GP/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_D_212GP
+	bool "D_212GP core"
+

arch/xtensa/soc/D_233L/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if D_108mini
+if SOC_D_233L
+
+config SOC
+	string
+	default D_233L
 
 config IRQ_OFFLOAD_INTNUM
 	default 7

arch/xtensa/soc/D_233L/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_D_233L
+	bool "D_233L core"
+

arch/xtensa/soc/XRC_D2PM/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if XRC_D2PM
+if SOC_XRC_D2PM
+
+config SOC
+	string
+	default XRC_D2PM
 
 config IRQ_OFFLOAD_INTNUM
 	default 11

arch/xtensa/soc/XRC_D2PM/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XRC_D2PM
+	bool "XRC_D2PM core"
+

arch/xtensa/soc/XRC_D2PM_5swIrq/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if XRC_D2PM_5swIrq
+if SOC_XRC_D2PM_5SWIRQ
+
+config SOC
+	string
+	default XRC_D2PM_5swIrq
 
 config IRQ_OFFLOAD_INTNUM
 	default 22

arch/xtensa/soc/XRC_D2PM_5swIrq/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XRC_D2PM_5SWIRQ
+	bool "XRC_D2PM_5swIrq (XRC_D2PM core with 4 additional SW IRQs)"
+

arch/xtensa/soc/XRC_FUSION_AON_ALL_LM/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi_mini
+if SOC_XRC_FUSION_AON_ALL_LM
+
+config SOC
+	string
+	default XRC_FUSION_AON_ALL_LM
 
 config IRQ_OFFLOAD_INTNUM
 	default 13

arch/xtensa/soc/XRC_FUSION_AON_ALL_LM/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XRC_FUSION_AON_ALL_LM
+	bool "XRC_FUSION_AON_ALL_LM core"
+

arch/xtensa/soc/hifi2_std/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi2_std
+if SOC_HIFI2_STD
+
+config SOC
+	string
+	default hifi2_std
 
 config IRQ_OFFLOAD_INTNUM
 	default 7

arch/xtensa/soc/hifi2_std/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI2_STD
+	bool "hifi2_std core"
+

arch/xtensa/soc/hifi3_bd5/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if XRC_FUSION_AON_ALL_LM
+if SOC_HIFI3_BD5
+
+config SOC
+	string
+	default hifi3_bd5
 
 config IRQ_OFFLOAD_INTNUM
 	default 13

arch/xtensa/soc/hifi3_bd5/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI3_BD5
+	bool "hifi3_bd5 core"
+

arch/xtensa/soc/hifi3_bd5_call0/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi3_bd5_call0
+if SOC_HIFI3_BD5_CALL0
+
+config SOC
+	string
+	default hifi3_bd5_call0
 
 config IRQ_OFFLOAD_INTNUM
 	default 13

arch/xtensa/soc/hifi3_bd5_call0/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI3_BD5_CALL0
+	bool "hifi3_bd5_call0 (hifi3_bd5 core with call0 ABI and 3 additional SW IRQs)"
+

arch/xtensa/soc/hifi4_bd7/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi4_bd7
+if SOC_HIFI4_BD7
+
+config SOC
+	string
+	default hifi4_bd7
 
 config IRQ_OFFLOAD_INTNUM
 	default 4

arch/xtensa/soc/hifi4_bd7/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI4_BD7
+	bool "hifi4_bd7 core"
+

arch/xtensa/soc/hifi_mini/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi3_bd5
+if SOC_HIFI_MINI
+
+config SOC
+	string
+	default hifi_mini
 
 config IRQ_OFFLOAD_INTNUM
 	default 13

arch/xtensa/soc/hifi_mini/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI_MINI
+	bool "hifi_mini core"
+

arch/xtensa/soc/hifi_mini_4swIrq/Kconfig.defconfig

@@ -4,7 +4,11 @@
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-if hifi_mini_4swIrq
+if SOC_HIFI_MINI_4SWIRQ
+
+config SOC
+	string
+	default hifi_mini_4swIrq
 
 config IRQ_OFFLOAD_INTNUM
 	default 1

arch/xtensa/soc/hifi_mini_4swIrq/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_HIFI_MINI_4SWIRQ
+	bool "hifi_mini_4swIrq (hifi_mini core with 4 additional SW IRQs)"
+

arch/xtensa/soc/sample_controller/Kconfig

@@ -1,12 +0,0 @@
-# Kconfig - XTENSA board configuration
-#
-# Copyright (c) 2016 Open-RnD Sp. z o.o.
-# Copyright (c) 2016 Cadence Design Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-if sample_controller
-
-config IRQ_OFFLOAD_INTNUM
-	default 7
-
-endif

arch/xtensa/soc/sample_controller/Kconfig.defconfig

@@ -0,0 +1,16 @@
+# Kconfig - XTENSA board configuration
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 Cadence Design Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SAMPLE_CONTROLLER
+
+config SOC
+	string
+	default sample_controller
+
+config IRQ_OFFLOAD_INTNUM
+	default 7
+
+endif

arch/xtensa/soc/sample_controller/Kconfig.soc

@@ -0,0 +1,6 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SAMPLE_CONTROLLER
+	bool "sample_controller core"
+

boards/xtensa/xt-sim/xt-sim_defconfig

@@ -1,5 +1,6 @@
 CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_IPM_CONSOLE_STACK_SIZE=2048
 CONFIG_XTENSA=y
+CONFIG_SOC_SAMPLE_CONTROLLER=y
 CONFIG_SIMULATOR_XTENSA=y
 CONFIG_CONSOLE=y

scripts/Makefile.toolchain.xcc

@@ -1,61 +1,47 @@
-XTENSA_ISS_CYCLES_LIMIT=1000000000 # Simulate 10^9 cycles.
+XTENSA_ISS_CYCLES_LIMIT := 1000000000 # Simulate 10^9 cycles.
+
 ifndef XTENSA_TOOLS_PATH
-$(error Please set XTENSA_TOOLS_PATH first)
+    $(error Please set XTENSA_TOOLS_PATH first)
 endif
+
 ifndef XTENSA_BUILDS_PATH
-$(error Please set XTENSA_BUILDS_PATH first)
+    $(error Please set XTENSA_BUILDS_PATH first)
 endif
-XTENSA_BUILD_DIR:=$(patsubst "%",%,${XTENSA_BUILD_DIR})
+
+XTENSA_BUILD_DIR := $(patsubst "%",%,${XTENSA_BUILD_DIR})
+
 ifeq (${XTENSA_BUILD_DIR},)
-XTENSA_BUILD=$(shell echo ${XTENSA_BUILDS_PATH}/${XTENSA_CORE})
+    XTENSA_BUILD=$(shell echo ${XTENSA_BUILDS_PATH}/${CONFIG_SOC})
 else
-ifeq ($(patsubst /%,/,${XTENSA_BUILD_DIR}),/)
-XTENSA_BUILD=${XTENSA_BUILD_DIR}
-else
-XTENSA_BUILD=$(shell echo ${CONFIG_XTENSA_BUILDS_PATH}/${XTENSA_BUILD_DIR})
-endif
+    ifeq ($(patsubst /%,/,${XTENSA_BUILD_DIR}),/)
+        XTENSA_BUILD=${XTENSA_BUILD_DIR}
+    else
+        XTENSA_BUILD=$(shell echo ${CONFIG_XTENSA_BUILDS_PATH}/${XTENSA_BUILD_DIR})
+    endif
 endif
+
 # Strip quotes from cross compiler anme prefix
 CROSS_COMPILE_xtensa=$(patsubst "%",%,${CONFIG_CROSS_COMPILE})
+
 ifeq (${CROSS_COMPILE_xtensa},)
-# Use default name prefix if no cross compiler name prefix is set
-CROSS_COMPILE_xtensa=xt-
+    # Use default name prefix if no cross compiler name prefix is set
+    CROSS_COMPILE_xtensa=xt-
 endif
 
 ifeq (${CONFIG_XTENSA},y)
-CROSS_COMPILE=${XTENSA_TOOLS_PATH}/bin/$(CROSS_COMPILE_$(ARCH))
+CROSS_COMPILE = ${XTENSA_TOOLS_PATH}/bin/$(CROSS_COMPILE_$(ARCH))
 
 ifeq ($(USE_CCACHE),1)
-CC=$(CCACHE) ${CROSS_COMPILE}xcc --xtensa-core=$(XTENSA_CORE)
-CXX=$(CCACHE) ${CROSS_COMPILE}xc++ --xtensa-core=$(XTENSA_CORE)
+    CC = $(CCACHE) ${CROSS_COMPILE}xcc --xtensa-core=$(CONFIG_SOC)
+    CXX = $(CCACHE) ${CROSS_COMPILE}xc++ --xtensa-core=$(CONFIG_SOC)
 else
-CC=${CROSS_COMPILE}xcc --xtensa-core=$(XTENSA_CORE)
-CXX=${CROSS_COMPILE}xc++ --xtensa-core=$(XTENSA_CORE)
+    CC = ${CROSS_COMPILE}xcc --xtensa-core=$(CONFIG_SOC)
+    CXX = ${CROSS_COMPILE}xc++ --xtensa-core=$(CONFIG_SOC)
 endif
-AS=${CROSS_COMPILE}as --xtensa-core=$(XTENSA_CORE)
-LD=${CROSS_COMPILE}ld --xtensa-core=$(XTENSA_CORE)
+AS = ${CROSS_COMPILE}as --xtensa-core=$(CONFIG_SOC)
+LD = ${CROSS_COMPILE}ld --xtensa-core=$(CONFIG_SOC)
 CROSS_COMPILE_TARGET = ${CROSS_COMPILE_TARGET_${ARCH}}
 
-#CORES
-XTENSA_CORES_LIST=$(shell sed -ne 's/^config \(.*\)/\1 /p' \
-						${ZEPHYR_BASE}/arch/xtensa/soc/Kconfig.cores)
-define XTENSA_CORE_CHECK
-
-ifeq ($$(CONFIG_$(strip $1)),y)
-XTENSA_CORE=$(strip $1)
-endif
-
-endef
-define XTENSA_CORES_CHECK
-$(foreach core,${XTENSA_CORES_LIST}, $(call XTENSA_CORE_CHECK, ${core}))
-endef
-
-$(eval ${XTENSA_CORES_CHECK})
-
-ifeq (${XTENSA_CORE},)
-$(error Failed to parse "arch/xtensa/soc/Kconfig.cores" for getting cores list)
-endif
-
 XTENSA_SYSTEM=$(XTENSA_BUILD)/config
 
 XTSC_INC=$(realpath $(patsubst "%",%,${CONFIG_XTENSA_XTSC_INC}))
@@ -93,8 +79,8 @@ KBUILD_CXXFLAGS:=$(filter-out \
 XTRUN=${CROSS_COMPILE}run
 XTRUN_FLAGS += --cycle_limit=${XTENSA_ISS_CYCLES_LIMIT}
 
-export CROSS_COMPILE XTENSA_CORE XTENSA_SYSTEM LIB_INCLUDE_DIR
-endif
+export CROSS_COMPILE XTENSA_SYSTEM LIB_INCLUDE_DIR
+endif # CONFIG_XTENSA
 
 prepare2:
 	${Q}test -d ${XTENSA_BUILD} || ( \

scripts/Makefile.xt-run

@@ -10,9 +10,9 @@ ifneq (${QEMU_PTY},)
 endif
 
 run: zephyr
-	@echo "**** Running simulation for Xtensa core \"${XTENSA_CORE}\" ****"
+	@echo "**** Running simulation for Xtensa core \"${CONFIG_SOC}\" ****"
 	$(if ${QEMU_PIPE},,@echo "To exit from XT-RUN enter: 'CTRL+c'")
-	@echo '[XT-RUN] CPU: ${XTENSA_CORE}'
+	@echo '[XT-RUN] CPU: ${CONFIG_SOC}'
 	# Run the emulator in the background and leave a PID file for
 	# sanitycheck
 ifneq ($(QEMU_PIPE),)

scripts/Makefile.xtsc-run

@@ -20,9 +20,9 @@ endif
 
 xtsc-run:run
 run:zephyr
-	${Q}echo "***** Running simulation for Xtensa core \"${XTENSA_CORE}\" *****"
+	${Q}echo "***** Running simulation for Xtensa core \"${CONFIG_SOC}\" *****"
 	$(if ${QEMU_PIPE},,@echo "To exit from XTSC-RUN enter: 'CTRL+c'")
-	@echo '[XTSC-RUN] CPU: ${XTENSA_CORE}'
+	@echo '[XTSC-RUN] CPU: ${CONFIG_SOC}'
 	${Q}test -f ${XTSC_INC} || ( \
 		echo '*** Error: $@ requires valid XTSC include file in \
 			"$${CONFIG_XTENSA_XTSC_INC}"' && \