NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently, the driver imply understand that all instances
will use dma when CONFIG_SPI_MCUX_LPSPI_DMA is set. There
might be an instance doesn't need DMA, so instead of enforce
spi_transceive API to use DMA, add more flexible to enable
DMA only when required
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Modify STM32H7 SPI driver so that it updates the rx/tx
pointers correctly (depending on the frame size) when DMA
is enabled. Also, make the dummy rx/tx buffer cache-coherent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
The way of setting a nocache region in devicetree has changed.
Adapt the H7 SPI driver to this new circumstance.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Drivers for nRF SoCs using pinctrl did not select PINCTRL. This means
boards are forced to enable PINCTRL.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Drivers should only log extra information during initialization if
debug logging is enabled. Otherwise it always clutters the console
when not required.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Zephyr version 3.4 changed the SPI context structure and macros
which broke the logic in the MEC172x SPI driver configuration API.
This was not detected by CI due to no tests for this driver are in
the tree. The driver now behaves like most other SPI drivers requiring
a different configuration structure pointer to be passed if any item
in the configuration changes.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Initial version of Infineon CAT1 SPI Driver supporting synchronous
and asynchronous data transfer API
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
When doing a TX-only SPI operation, the RX not empty flag will never get
set, thus this will just hang forever.
Found/tested on STM32L462 trying to drive some WS2812 RGB LEDs.
Signed-off-by: David Lamparter <equinox@diac24.net>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Check the TXC flag instead of EOT for the case of endless
transactions (TSIZE = 0), which in this case is always as
the stm32 SPI driver doesn't set TSIZE.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
CONFIG_NOCACHE_MEMORY is a valid way of declaring buffers in
nocache regions. Consider them valid in the stm32 SPI driver
nocache check. Also, don't check NULL buffers as the SPI
interface states that such buffers will result in sending
zeroes.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
This is a follow-up to commit fa609e5844.
This driver implements SPI slave operations only and cannot be used
without the corresponding Kconfig option enabled.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Following #56576, the `cs` field in `struct spi_config` is of type
`struct spi_cs_control` instead of a pointer to the same type.
This PR updated the driver to use `spi_cs_is_gpio()` helper to
check if SPI CS is controlled using a GPIO.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Removes the shadow variable found by -Wshadow. The value of this
variable is the same throughout the for loop, so there is no
need to assign it again for each iteration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Pin state after SPI deinitialization is based on pinctrl configuration.
On the other hand, CPOL is set during runtime. When the SPI instance
is disabled GPIO takes control over SCK and drives it to state set
by pinctrl driver. This might causes an invalid SCK state
when the transaction is configured with CPOL (Clock Polarity).
To address this issue, a patch was introduced to the SPI driver.
Now, when a SPI instance is configured with CPOL,
the driver is setting in the runtime the correct state of the SCK pin.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Pin state after SPIM deinitialization is based on pinctrl configuration.
On the other hand, CPOL is set during runtime. With the introduction
of the power-optimized SPIM driver, it disables the peripheral instance
once the transfer is completed.
As a result, the GPIO takes control over the SCK pin and drives it
based on pinctrl configuration which causes an invalid SCK state
when the transaction is configured with CPOL (Clock Polarity).
To address this issue, a patch was introduced to the SPIM driver.
Now, when a SPIM instance is configured with CPOL,
the driver is setting in the runtime the correct state of the SCK pin.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
ESP32 SoC refactoring added new SOC_SERIES definition,
which was missed by #60183. This fixes it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
SPI driver is current working for common SPI devices.
However, addressable LED like WS2812 requires MOSI line to be
default LOW during initialization. This PR adds such option.
This has no effect on common SPI operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Refactor the function to make the execution flow in transceive()
clearer. In particular, return error codes directly, not through
spi_context_complete() which is unnecessary in this case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
DMA only works with non-cached memory regions in H7. Check them
and return an error if they don't match this condition.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
This is a follow-up to commit 4c20403629.
CONTAINER_OF() cannot be used to obtain the device pointer from its
data pointer as this data is not contained in the device structure.
Instead, use a dedicated member in the device data structure to store
the device pointer.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The MCUX DMA controller only supports a single data_size
for a DMA transfer, not separate ones for source and
dest. An older version of the DMA driver used
dest_data_size as the DMA transfer size, but the
current one uses MIN(dest/source) as the trasnfer
size, which breaks case when SPI wants to do 2-byte
transfers.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The `spi_mcux_transceive` had 2 return calls when the
`CONFIG_SPI_MCUX_LPSPI_DMA` flag was active. The first return would be
called and the later was unreachable. With the fix, now the return calls
are mutually exclusive. Also, the `transceive` call is not compiled with
the `CONFIG_SPI_MCUX_LPSPI_DMA` flag is active.
Fixes#59533
Signed-off-by: Dipak Shetty <dipak.shetty@zeiss.com>
The eSPI, I2C, and SPI emulators use devicetree macros to build an array
of devices on the virtual bus. Currently, they will add device nodes that
are not status-okay. This leads to linker errors because the respective
device drivers would not have instantiated device structs for these
nodes --assuming the driver was even compiled. This can be frustrating
if nodes need to be disabled for debugging or configuration purposes.
Update the bus emulators to only consider status-okay nodes by changing
the macros used to iterate over bus devices.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Fix for bug:
https://github.com/zephyrproject-rtos/zephyr/issues/59575
The dma version of the version of the driver can
invoke multiple intermediate dma transfers, like
when the spi_buf_set count is greater than one.
However, there is a bug where chip select is not kept
asserted for all intermediate dma transfers required
to process the entire spi_buf_set.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Replace the timeout for a SPI transceive in slave mode for STM32 DMA
operations with a K_FOREVER. Being an SPI slave means we do not
know when the transaction will start, hence it does not make sense
to have a timeout in such a case.
This will resolve issue #60000.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The `SPI_EMUL_INIT(n)` macro used to instantiate SPI bus emulators
builds an array of SPI devices attached to the bus, but always checks
instance #0 of the bus and not `n`. This makes multiple instances of an
emulated SPI bus unusable and popualtes them all with bus 0's devices.
Change the `0` to `n`, which matches how the I2C bus emulator does it.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Found EMSDP board SPI-FLASH sample broke after adding DFSS
into spi_dw. Found wrong interrput mask resulting in false
interrupt enabled. Now fixed it to fit both DFSS and DW.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI
driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll
SPI-Flash and DFSS SPI to connect external devices. Both drivers
share most source code, but DFSS uses ARC auxiliary registers.
Move FIFO depth setting to device tree.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Commit 246393e830
("drivers: spi: spi_nrfx_spim: Remove nrf_frequency_t handling")'
introduced two changes, one of them is removing the function
get_nrf_spim_frequency with a strange justification.
This change breaks support for peripherals written in a common way,
where the maximum frequency is set to the maximum supported
by the peripheral, not the controller, see shields for example.
On the occasion of bringing it back, the original function was
refactored to be easier to read and understand.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add driver for OpenTitan SPI host.
Tested and verified single SPI full duplex on opentitan_earlgrey in
Verilator.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Rather than the rings, which weren't shared between userspace and kernel
space in Zephyr like they are in Linux with io_uring, use atomic mpsc
queues for submission and completion queues.
Most importantly this removes a potential head of line blocker in the
submission queue as the sqe would be held until a task is completed.
As additional bonuses this avoids some additional locks and restrictions
about what can be submitted and where. It also removes the need for
two executors as all chains/transactions are done concurrently.
Lastly this opens up the possibility for a common pool of sqe's to
allocate from potentially saving lots of memory.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
