Having a per-instance init function makes code cluttered and hard to
read. Just create a per-instance IRQ connect function (required to
resolve IRQ_CONNECT parameters at compile time).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using NRFX_SPI(S|M)_INSTANCE helper so that peripheral address from
Devicetree is used. We should not rely on HAL for hardware description
but Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move the RX (MISO) delaying capability information to Devicetree. It is
done using 2 properties:
- rx-delay-supported: enabled on SPI nodes that support delaying RX.
This property can be used by the driver to determine if this
capability is supported or not on a given instance.
- rx-delay: the actual RX delay value
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The maximum transfer buffer length is SoC specific, not instance
specific. This patch defines MAX_BUF_LEN at driver level in a SoC
specific manner instead of using HAL values that are instance specific
but that always take the same value depending on the SoC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The maximum transfer chunk length is SoC specific, not instance
specific. This patch defines MAX_CHUNK_LEN at driver level in a SoC
specific manner instead of using HAL values that are instance specific
but that always take the same value depending on the SoC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the overrun character in Devicetree. Since 0xFF is the most
common value, DT property contains such default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Devicetree is the natural place to describe hardware, so move the
maximum frequency the SPI can work with to Devicetree instead of relying
on values from HAL.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
DT nodes aren't guaranteed to define a label property. But emulated bus
controllers currently make use of this property to dispatch to the
associated emulator.
Have emulated bus controllers use DEVICE_DT_GET(node_id) to dispatch to
right target peripheral emulator. This also change makes emul_get_binding
and device_get_binding synonymous in behavior with respect to their
parameters.
This also strictly enforces a 1:1 correspondence between invocations of
DEVICE_DT_DEFINE and EMUL_DEFINE.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Allow emulator creators to write an init function that can be used
across multiple busses so as to reduce the boilerplate and cognitive
load in creating an emulator.
Part of this change includes allowing access to the emul struct from a
field in a {bus}_struct api (e.g. i2c_struct), which removes the need for
sporadic usages of CONTAINER_OF to access the emul struct.
Overall, this change simplifies and reduces the amount of boilerplate
code to get a device emulator up and running, thus reducing excise work
to writing tests.
TEST=twister on accel,espi, and eeprom drivers tests
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Run clang-format on all files touched by improved emulator API pull-request
that allowed access to the target device emulator from its bus api without
CONTAINER_OF usage.
drivers/i2c/i2c_emul.c
drivers/spi/spi_emul.c
include/zephyr/drivers/emul.h
include/zephyr/drivers/espi_emul.h
include/zephyr/drivers/i2c_emul.h
include/zephyr/drivers/spi_emul.h
subsys/emul/emul.c
subsys/emul/emul_bmi160.c
subsys/emul/espi/emul_espi_host.c
subsys/emul/i2c/emul_atmel_at24.c
TEST=twister on accel,espi, and eeprom drivers tests
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Implement support for half duplex communication in the bit bang SPI
driver. The SPI driver will use the MOSI pin is for both TX and RX
operations when using half duplex mode.
In half-duplex mode, the driver configures the MOSI pin as an input
pin for input only transactions. Transactions that are bidirectional
are forbidden. After an SPI transaction, the MOSI pin is left as an
input if it was an RX transaction or an output after a TX
transaction. Like before, the MOSI pin is initialized as an
(inactive) output pin when the bus is initialized.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.
This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
spi_context_cs_configure_all() is currently called from
spi_bitbang_transceive(). This causes a glitch when combined with
SPI_HOLD_ON_CS is used.
Move the initialization to spi_bitbang_init which is what the other
SPI drivers seem to do.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SPI bitbang driver doesn't correctly initialize the list of CS
GPIOs. As a consequence, SPI buses using the bitbang driver won't
drive CS low. Add the missing initialization.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.
This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds driver for the Microchip Polarfire SOC MSS QSPI
controller.
The interrupts of the MSS QSPI are routed through PLIC(Platform level
interrupt controller).
Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The SPI peripheral on SiFive parts uses FIFOs for Rx and Tx (FIFO size
undocumented, but empirically found to be 8 bytes on FE310, likely
identical on FU540 / FU740). Make use of these FIFOs in order to
continuiously feed Tx data as available.
Verified to transmit 1 MHz SPI @ 200 MHz coreclk / tlclk on FE310
continuously without downtime between frames.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
spi_context uses uint8_t buffers, and HW rxdata / txdata registers only
contain 8 bits of data (along with b31 full / empty flag), so uint8_t is
appropriate.
Suggested-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use the dedicated `DT_INST_STRING_TOKEN` macro instead of manually
retrieving `DT_DRV_INST`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add support for an alternate clock. If available,
alternate clock is enabled and used to get the
device clock rate.
Fixes#41650
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.
Refactor device tree macros usage to make usage of
SPI instances more general.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
The SAM0 fast-path implementation was broken, and partially fixed in
commits 8181eed and 8a99bd0...
This patch resolves an issue where the MSB is always zero on SAML21
parts, and appears to follow suit with the previous patches.
This patch also refreshes the commentary, and removes mention of the
"interleaved" operation that is no longer used - which appears to have
been problematic in the past.
In addition to this, it also resolves an off-by-one error in both the
fast_rx and fast_rxrx paths, which would have been tripped when
transmitting a zero-byte buffer.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.
This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
ESP32C3 requires master init call to enable its clock
gate. Without this, SPI interface may not initialize
properly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Don't use the old gpio_dev spi_cs_control's member
since it's been deprecated in favor of gpio_dt_spec.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This add support to pinctrl at Atmel sam0 spi driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam spi driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
