Set the LTDC buffer alignment to 256 in order to avoid an
issue when accessing to PSRAM via XSPI.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Several subsystems have configuration options that allow large buffers
to be placed in specialized memory sections. When PSRAM is enabled, the
MBEDTLS heap and LVGL heap and buffer can be relocated to custom sections
within the PSRAM segment.
Enabling `CONFIG_ESP_SPIRAM` together with any of the following options:
* `CONFIG_MBEDTLS_HEAP_CUSTOM_SECTION`
* `CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION`
* `CONFIG_LV_Z_VDB_CUSTOM_SECTION`
will place the corresponding buffers into the `.mbedtls_heap`,
`.lvgl_heap`, and `.lvgl_buf` sections, respectively.
If none of these custom section options are enabled, the buffers will
fall back to the `.ext_ram.bss` section.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Increase the long workqueue stack size to prevent it from being
overflown for example in the GATT database hashing. This leaves
us with a bit less than 200B of headroom as of today
Signed-off-by: Jori Rintahaka <jori.rintahaka@silabs.com>
Struct girq_regs has an array field of length 1 at its end. Since this
field is never used in the code base, we can replace it with a non-array
field of its original element type to remove the flexible-array-like
behaviors and avoid using a flexible array file in the middle of a
struct or defining an array of flexible array struct type.
Fixes zephyrproject-rtos#84251
Signed-off-by: Ella MA <xutong.ma@inria.fr>
Set regulatory domain to default US for IW610 and RW610 socs
and WW for IW416 and IW612 socs.
Signed-off-by: Abhinav Kulkarni <abhinav.kulkarni@nxp.com>
Add a linker script for the stm32mp2x soc series. It includes the
standard arm cortex-m linker and adds standard zephyr relocation
sections.
Replace the rom_start section name with .isr_vectors in the linker
script. This is necessary for the zephyr firmware to be started by the
remote proc driver which expects the section containing the vector table
to be named .isr_vectors.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add initial soc support for the stm32mp2x series, including
initial Kconfig entries and default configuration files.
This enables Zephyr to recognize and build for the stm32mp2x series,
taking the stm32mp257f_ev1 as a baseline.
Includes:
- Kconfig and defconfig files for SoC selection and defaults
- soc.h for hal headers
- CMakeLists.txt for build system integration
- soc.yml update to register the new SoC
System Clock is configured statically from DTS. So no initialization
hook or soc.c needed.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add initial support for Renesas RZ/V2N
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Some devices have multiple pinctrl regions; for instance, main pinctrl and
mcu pinctrl. Currently there can only be a single pinctrl instance picked
form a DT label. This patch makes the pinctrl driver initialise one
instance for each node with correct compatible string.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Added support for deriving `SYS_CLOCK_HW_CYCLES_PER_SEC` from the
Device Tree by reading the `clock-frequency` property in the `itim` node.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
The driver originally supported only it8xxx2 series. This updates
introduces compatibility allow it to also support it51xxx series
with minimal changes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Disable support to local ISR declaration on Espressif SoCs.
Code relocation is not yet supported, causing build fail.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
If a bootloader is used, it will configure the SMU and SAU.
The application cannot also configure it, since it can't know
what alias (S vs NS) to access the CMU through. Only connect
the interrupt to the application's vector table if a bootloader
is present.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for configuring the power/performance
profile for the siwx91x device using a generic
'power-profile' property in DeviceTree.
The property is available for NWP nodes,
allowing flexible selection of power management
profiles per application or board via overlay.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add UARTE23 and UARTE24 missing Kconfig options and their
translation to NRFX configuration macros.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
The STM32 signing tool (STM32_SigningTool_CLI) is invoked as a post-build
command to generate a signed Zephyr binary, which is required to run from
flash on N6 series. If the file specified as output already exists, the
tool will by default prompt to confirm it should be overwritten. However,
when invoked from the build system rather than a terminal, this prompt
will break the build (freeze during the "Linking zephyr.elf" step). This
can be seen by building the same application twice in a row, as the second
build will not be different enough to make the build artifacts be deleted
and thus the (old) signed image will be seen by the tool.
Invoke the tool in silent mode such that user is never prompted. This fixes
build failures while still working as intended (if present, the existing
signed image will get overwritten properly).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Restore main stack size to the default value since fake entropy
implementation from mbedtls is replaced by STM32 entropy driver.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
NFCT is by default assigned to application so DT node does
not need to be enabled or reserved in DT to have access to
NFCT registers. On cpurad NFCT must be reserved to enable
register access and then antenna pins can be configured as
gpios.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
CM33 must write MEMCONF.POWER[VPR].RET = 0 before entering System OFF.
This bit drives the vprSavedCtx input to VPR. Forcing it low will
disable the Hibernate wake feature in VPR, so that VPR will remain
in its reset state when waking from OFF.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
On ACE30 platforms adding a section to the linker script isn't
enough, it should also be added to the xtensa_soc_mmu_ranges[] array.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On dual-core STM32H7, the Cortex-M4 core is supposed to wait until the
Cortex-M7 initializes the system before starting to execute. CM7 should
signal this by locking a specific HSEM, which CM4 should poll until locked.
However, the logic on the Cortex-M4 side was reading the "RLR" register of
HSEM, which *locks the semaphore on read* - in turn, this makes the CM4
start directly since it sees that the semaphore is locked (by itself).
Use proper LL API to read HSEM status - which will read the "R" register
instead - to make sure CM4 doesn't begin execution earlier than it should.
Suggested-by: hglassdyb
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on
STM32H7 to synchronize the two cores. Update the comment above the SEMID
define to reflect this alternate usage. Also remove the associated define
CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add MPS4 pinctrl support by referring to
`mps4/common/partition/platform_base_address.h`
from TF-M's main branch.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add initial support for the MPS4 Corstone-320 platform, including board
and SoC definitions. This platform features a Cortex-M85 CPU with an
Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320
Fixed Virtual Platform.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
