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soc: neorv32: the NEORV32 does not fully support ISA A extension

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The NEORV32 v1.8.6 does not fully support the RISC-V ISA A
extension. Remove it and enable support for atomic operations in C
regardless of the version used.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2025-02-23 18:55:12 +00:00 • committed by Benjamin Cabé
commit 8662e0fdcb
1 changed files with 3 additions and 4 deletions
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7
soc/neorv32/Kconfig
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@ -1,23 +1,22 @@
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
config SOC_NEORV32
select RISCV
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
select ATOMIC_OPERATIONS_C
imply XIP
if SOC_NEORV32
config SOC_NEORV32_V1_8_6
bool "v1.8.6"
# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
select ATOMIC_OPERATIONS_C
config SOC_NEORV32_VERSION
hex