On ACE30 platforms adding a section to the linker script isn't
enough, it should also be added to the xtensa_soc_mmu_ranges[] array.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This patch makes cosmetic changes to cavs/power.c by updating comments to
Doxygen style, fixing typos.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch makes cosmetic changes to ace/power.c by updating comments to
Doxygen style, fixing typos, and removing an extraneous character for
improved readability and consistency.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch enhances the power management capabilities of the Intel ADSP
by ensuring that power gating states are appropriately managed based on
core activity. It prevents the primary core from entering power gating
if secondary cores are active and re-enables power gating when all
secondary cores are off, using pm_policy_state_lock_get and
pm_policy_state_lock_put functions.
The Sound Open Firmware (SOF) project currently uses a custom power
management policy to achieve these effects. With this patch, the default
power management policy can be utilized, allowing the option to disable
the custom policy while maintaining system reliability and performance
across different core states.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
There is no need for kernel/internal/smp.h as SOF does not call
z_sched_ipi(). Actually... git log over there has no mention of
z_sched_ipi() anywhere, just arch_sched_ipi().
And include <ksched.h> for source using z_sched_ipi() since
they are using scheduling functions, and would be the correct
file to include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Intel Audio DSP ACE needs to use arch_spin_relax() to give
the bus more time to propagate the RCW transactions among
CPUs, and to avoid sending too many requests to the bus
after failing to lock spinlocks. However, the number of
NOPs results in a very big arch_spin_relax() that spans
multiple instruction cache lines, and requires evicting
them just for NOPs. With 5 CPUs, it can span 6 cache
lines (if using nop.n instead of nop). That's a waste of
space and cache. So instead, we do a tight loop instead.
Since the SoC supports zero-overhead loops, this should
have minimal performance impact.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some weird unknown reasons, the simulator really do not
like the cpuhold_* variables to be tightly packed together.
This results in cpuhold_spawned not being updated, and we
will be stuck in the while loop for it to be set.
Workaround this by explicitly aligning these variables on
16 byte boundary. This seems to work for now.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will set MMU permissions for .cold* sections
Fixes cold section execution if MMU is enabled
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
MD5 and SHA1 are not supposed to be used nowadays on security context.
Some ancillary scripts in tree do use them, but for verification only -
or where externally mandated, such the SPDX tool.
This patch marks those usages as `usedforsecurity=False`, which helps
clarify intent.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
CONFIG_ADSP_POWER_DOWN_HPSRAM may not be defined (when it's "n") so
update the code accordingly so that power_down() is called with
correct parameters.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
If no PCI device with DSP capability is reported, also try to
find compatible devices using PCI_CLASS=40300. This is mostly
useful on preproduction systems where incorrect PCI class data
is reported.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Add support for .cold and .coldrodata sections, used to implement
a cold module. Assigning code and read-only data to those sections
makes them suitable for use in a cold module, stored and executed in
slow memory.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add a manifest for a "cold" module, that will be executed in DRAM
without copying it to SRAM for the whole duration of the firmware
life-time.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Before copying modules to SRAM, check whether they're built for it,
skip modules, that aren't.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This reverts commit 3d3ffa2c05.
The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.
Reverting this commit restores access to these critical registers and
resolves the regression issue.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This puts the syscall helpers into the vector code section, and
is a tiny TLB optimization. Before this, worst case scenario is
that there would 2 instruction TLB misses when both the syscall
helpers and the vector code pages are not in TLB cache. With
this change, there would be at most 1 instruction TLB miss as
now the syscall helper and the vector code (which includes
exception handling code and xtensa_do_syscall()) are now in
the same page, and the same TLB entry.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The MMU mapping in SoC covers 0x0 which prevents catching NULL
pointer accesses. Since there are no hardware registers at
the very first page of memory, we move the starting point one
page later.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace hardcoded register addresses and values in
asm_memory_management.h with Devicetree (DT) macros for LPSRAM
power-down operations. This change ensures that register addresses and
bank counts are dynamically obtained from the Devicetree, improving code
portability and reducing the risk of errors due to manual updates.
- Removed hardcoded LSPGCTL address definitions.
- Updated m_ace_lpsram_power_down_entire macro to use DT_NODELABEL to
fetch LPSRAM bank count and control register address
- Adjusted bit field extraction logic to align with the updated register
information from the Devicetree.
This commit aligns with the ongoing effort to utilize Devicetree for
hardware abstraction and to facilitate easier maintenance and updates to
the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the m_ace_hpsram_power_change macro from asm_memory_management.h
as it is no longer used after refactoring the power_down function to
utilize the new m_ace_hpsram_power_down_entire macro. This cleanup helps
to reduce code complexity and maintainability.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Refactor the power_down function to utilize the newly introduced
m_ace_hpsram_power_down_entire macro for shutting down the entire
HPSRAM. This change simplifies the power-down process by replacing the
previous segment-based power gating mask approach with a single boolean
flag that indicates whether the entire HPSRAM should be disabled.
The function signature of power_down has been updated to accept the new
boolean flag, and the corresponding call sites have been modified to
pass the flag based on the CONFIG_ADSP_POWER_DOWN_HPSRAM Kconfig option.
Additionally, the assembly code has been cleaned up to remove the
now-obsolete hpsram_mask array and related logic.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce a new assembly macro, m_ace_hpsram_power_down_entire, which
utilizes Zephyr Devicetree macros to power down the entire HPSRAM on
Intel ADSP ACE platforms.
This macro dynamically retrieves the HPSRAM bank count and control
register address from the Devicetree, streamlining the power-down
process. The macro is designed to iterate over all HPSRAM banks and
issue a power down command to each, ensuring a complete shutdown of the
HPSRAM when required by the system's power management policy.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit improves the readability of the power_down.S assembly file
by standardizing the indentation of the preprocessor definitions.
No functional changes have been made; this is purely a cosmetic update
to the code formatting.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit addresses an issue on platforms with an MMU where a
LoadStoreTLBMissCause exception occurs when accessing hardware registers
during the power-down process. The exception arises when attempting to
access the IPC register after HPSRAM has been powered down, leading to a
double exception: LoadStoreTLBMissCause followed by
InstrPIFDataErrorCause.
To resolve this, we preload the IPC register before shutting down
LPSRAM. This change prevents the double exception by ensuring that the
page table entries are correctly managed in the TLB before HPSRAM is
powered down and allowing the power-down sequence to complete
successfully.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fix definition for ROM status register for ACE1.5. The value should be
same as ACE2.0 and only different for ACE3.0.
Fixes: 6ad9b6ccab ("soc: intel_adsp: tools: add intel_adsp_ace30
support to cavstool.py")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Add debug_slot_offset_by_type() for getting debug window slot offset
by type identifier. How to find the correct slot and what types there
are is documented here:
soc/intel/intel_adsp/common/include/adsp_debug_window.h
In a normal situation a client program would try to find a specific
slot right after DSP boot. Because of that the we can not expect it to
be there immediately. Instead we need to try multiple times and give
firmware some time to update the debug slot descriptor table.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
The fw_is_alive() depends on 'dsp' global variable which is assigned
from map_regs() return value. To make fw_is_alive() and
wait_fw_entered(), that calls fw_is_alive(), callable from another
module, the 'dsp' variable needs to be passed as an argument.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
map_reg() depends on args global variable for knowing it should
load a new firmware or just stand by for logging or Zephyr
shell. The map_regs() code is the very first step to access the
DSP memory, it nees to be shareable if the code is to be accessed
from another python module.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
Do not force argsparse code to all modules importing cavstool.py. The
commit moves argparse code into a separate function, and calls it from
'if __name__ == "__main__":'. Also adds the argsparse call to to
acetool.py that shares cavstool code with the argument parsing.
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
